Bus control circuit for latching and maintaining data independen

Details Bus control circuit for latching and maintaining data independen Bus control circuit for latching and maintaining data independen

1990-04-09

1993-07-20

Lee, Thomas C.

Boots, shoes, and leggings

364DIG2, 36492691, 36492792, 36493541, 36493542, 36424291, 364DIG1, 395250, 370 851, G06F 1336

Patent

active

052300676

ABSTRACT:
In a means and method for optimizing bus utilization with traditional computer system components, one or more latch circuits are coupled to a computer data bus. The latch circuits latch data states on the data bus after the bus has been driven to a desired state by a system driver node. Tri-state drivers are preferred. Once a data state has been latched, the associated driver may be disabled without affecting the data state on the bus. The data state may then be sampled at any time, and the integrity of the data state is preserved, until a new data state is driven onto the bus by a driver node. The latch circuit parameters allow any system driver to readily overcome the latch action, yet preserve the driven data state as logically valid until it is overwritten. Data sampling from the bus is restricted solely during driver enable periods. Bus utilization is optimized without undue sacrifices in system power requirements.

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