Bus configuration validation for a multiple source disk array bu

Details Bus configuration validation for a multiple source disk array bu Bus configuration validation for a multiple source disk array bu

1991-03-14

1995-07-04

Canney, Vincent P.

Excavating

371 295, G06F 1100

Patent

active

054307473

ABSTRACT:
An interrupt signal indicating the existence of a bus configuration error within a disk array system is generated by monitoring the enable signals controlling bus drivers included in the array system. The array configuration error detector includes bus configuration error detection logic for each multiple-source bus within the array. Each bus configuration error detector is connected to receive all enable signals for the bus drivers associated with one bus and decode the received enable signals to generate an error signal when more than one of the received enable signals is active. The error signals generated for each of the multiple-source busses are provided to an adder and combined to form the configuration error interrupt signal for the array.

REFERENCES:
patent: 4918696 (1990-04-01), Purdham et al.
patent: 4953167 (1990-08-01), Byers et al.
Computer Architecture and Organization by John P. Hayes .COPYRGT.1988, McGraw-Hill Inc. pp. 475-479.

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