Bus circuit for eliminating undesired voltage amplitude

Details Bus circuit for eliminating undesired voltage amplitude Bus circuit for eliminating undesired voltage amplitude

1988-03-21

1989-10-03

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

307443, H04J 314

Patent

active

048721611

ABSTRACT:
A bus circuit capable of realizing a high speed data transfer cycle by eliminating undesired voltage amplitude of the data bus lines, includes a plurality of data bus lines, a potential initializing circuit for setting the initial potential of these data bus lines, an output port circuit for delivering data to these data bus lines, and an input port circuit for feeding data from these data bus lines. At least one of the data bus lines is a potential sensing line, and the sensing line is coupled to an inverting output circuit for inverting the initial potential from the output port circuit, and the potential change of this inverting output means is detected by a data firm judging means connected to the sensing line, and the output port circuit is deactivated by a control circuit in accordance with a judgement signal from the data firm judging circuit.

REFERENCES:
patent: 4627032 (1986-12-01), Kolwicz et al.
patent: 4638311 (1987-01-01), Gerety
patent: 4646272 (1987-02-01), Takasuki
patent: 4674083 (1987-06-01), Rackin
patent: 4679192 (1987-07-01), Vanbrabant
patent: 4744076 (1988-05-01), Elias

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