Bus circuit

Details Bus circuit Bus circuit

2011-01-18

2011-01-18

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C713S300000

Reexamination Certificate

active

07872517

ABSTRACT:
Clock control is handed over in a bus circuit from a first circuit (14) to a second circuit (12). A clock conductor (10a) is driven to a predetermined voltage level with the driver circuit of the first circuit after a last clock period following the start of execution of the handover command and to continue driving the clock conductor (10a) to the predetermined voltage level for a first time-interval. The clock conductor (10a) is driven to the predetermined voltage level with the driver circuit of the second circuit after a second time interval following the start of execution of the handover command until a third time interval has elapsed following the end of the second time interval. Subsequently the clock conductor (10a) is driven under control of the clock circuit (140) of the second circuit (14). The first time interval contains a first integer number P1of periods of a first clock signal of the first circuit and the second and third time interval contain a second and third integer number P2, P3of periods of a second clock signal of the second circuit, a duration corresponding to the second integer number P2equaling at least a pulse duration of the first clock signal, a duration corresponding to the first integer number P1equaling at least a duration corresponding to the second integer number P2plus one, a duration corresponding to the second plus third integer P2, P3equaling at least a duration corresponding to the first number P1plus one.

REFERENCES:
patent: 5317693 (1994-05-01), Cuenod et al.
patent: 5377189 (1994-12-01), Clark
patent: 5455916 (1995-10-01), Bourke et al.
patent: 5555381 (1996-09-01), Ludwig et al.
patent: 5732225 (1998-03-01), Miller et al.
patent: 5978658 (1999-11-01), Shoji
patent: 6418979 (2002-07-01), Lewis et al.
patent: 6597197 (2003-07-01), Mosley et al.
patent: 6721564 (2004-04-01), Kobayashi
patent: 6839393 (2005-01-01), Sidiropoulos
patent: 7010071 (2006-03-01), Michel et al.
patent: 7240145 (2007-07-01), Holman
patent: 7365566 (2008-04-01), Aoyama et al.
patent: 7447588 (2008-11-01), Xu et al.
patent: 7466784 (2008-12-01), Sidiropoulos
patent: 7489756 (2009-02-01), Sidiropoulos
patent: 7548601 (2009-06-01), Sidiropoulos
patent: 7570726 (2009-08-01), Sidiropoulos
patent: 7693288 (2010-04-01), Mergler
patent: 2005/0057292 (2005-03-01), Sidiropoulos
patent: 2006/0154710 (2006-07-01), Serafat
patent: 2007/0173212 (2007-07-01), Mergler
patent: 2009/0045854 (2009-02-01), Sidiropoulos
patent: 2009/0085631 (2009-04-01), Lambrecht et al.
patent: 2009/0132835 (2009-05-01), Ehmann
patent: 2009/0236909 (2009-09-01), Aldag et al.
patent: 2009/0285184 (2009-11-01), Watanabe et al.
patent: 2010/0069059 (2010-03-01), Nakagaki et al.
patent: 0 051 332 (1982-05-01), None
patent: 0 693 729 (1996-01-01), None
International Search Report dated Jun. 11, 2008 in connection with International Patent Application No. PCT/IB2006/053249.
Written Opinion of the International Searching Authority dated Jun. 11, 2008 in connection with International Patent Application No. PCT/IB2006/053249.

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