Bus bridge for responding to received first write command by sto

Details Bus bridge for responding to received first write command by sto Bus bridge for responding to received first write command by sto

1997-01-15

1998-06-16

Meky, Moustafa M.

G06F 1342

Patent

active

057685487

ABSTRACT:
A bus with bus commands which optimize the management of buffers within a bus bridge is disclosed. The bus incorporates at least two types of write commands, a Postable Memory Write command and a Memory Write command. The Postable Memory Write command serves as a write command which additionally instructs the bus bridge that the processor will not be informed that the data transfer is complete, and thus, data may be posted in the bus bridge. In contrast, the Memory Write command serves as a write command which additionally instructs the bus bridge that the processor may be informed that the data transfer is complete, and that data should not, accordingly, be posted. These two write commands are used in combination such that a data transfer of a contiguous block of data utilizes Postable Memory Write commands until the final transaction in the transfer, at which time, a Memory Write command is used. The bus further incorporates at least two types of read commands, including a Memory Read Prefetch command and a Memory Read command. The Memory Read Pre-fetch command serves as a read command which additionally instructs the bus bridge to pre-fetch a first amount of data. The Memory Read command serves as a read command which additionally instructs the bridge to pre-fetch a second amount of data, or in an alternative usage, to read the data without pre-fetching.

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