Bus architecture for digital signal processor allowing time mult

Details Bus architecture for digital signal processor allowing time mult Bus architecture for digital signal processor allowing time mult

1996-07-29

1997-03-11

Coleman, Eric

Boots, shoes, and leggings

3642448, 3642436, 364243, 364DIG1, G06F 1300

Patent

active

056110758

ABSTRACT:
A monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port. The digital signal processor may include one or more serial ports and one or more link ports for point-to-point communication with external devices. A DMA controller controls DMA transfers through the external port, the serial ports and the link ports.

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