Bus arbitration in a dual-bus architecture where one bus has rel

Details Bus arbitration in a dual-bus architecture where one bus has rel Bus arbitration in a dual-bus architecture where one bus has rel

1991-08-23

1994-11-29

Ray, Gopal C.

Multiplex communications

Wide area network

Packet switching

370 856, 3408255, 3642426, 36424292, 364240, 3642402, 364DIG1, G06F 1336

Patent

active

053697480

ABSTRACT:
A dual-bus architecture that includes a high-seed system bus, called the NexBus (20), and a slower peripheral bus, called the alternate bus or AB (25). The NexBus and AB are coupled by control logic (45) which includes an arbiter (50) and an alternate bus interface (ABI) (60). The ABI is treated as a master for both the NexBus and the AB. While it would be possible to have the adapter always request the AB (which also requires the NexBus), that would slow down NexBus operations to the bandwidth of the AB. This problem is avoided by providing two request lines for each adapter, -NREQ (NexBus only) and -AREQ (both buses), having the adapter normally assert -NREQ first. However, if the addressed device is on the AB, the ABI automatically detects this fact and attempts to do a crossing transfer to the AB, even though the request was for the NexBus only. If the ABI is unable to do the crossing transfer because the AB was busy, the ABI automatically causes the NexBus adapter to retry the request using the -AREQ line. Thus the slower AB is only accessed when actually necessary.

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