Bus arbitration between an I/O device and processor for memory a

Details Bus arbitration between an I/O device and processor for memory a Bus arbitration between an I/O device and processor for memory a

1995-12-08

1999-03-23

Ellis, Richard L.

395292, 395298, G06F 1318

Patent

active

058871950

ABSTRACT:
In an information processing system comprising an input/output device, a main memory device, a processing device including a first-in first-out type write-in buffer, and a bus connecting thereamong, the first-in first-out type write-in buffer comprises a flag bit holding area for holding a bus release request signal from the input/output device as a flag bit to produce the flag bit as a flag signal. The bus arbitration circuit determines the bus available right so as to grant a priority right for data write-in processing by the input/output device rather than data write-in processing by the processing device when the bus arbitration circuit receives the flag signal. The bus arbitration circuit determines the bus available right on the basis of the bus release request and the flag signal.

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patent: 4602327 (1986-07-01), LaViolette et al.
patent: 4703420 (1987-10-01), Irwin
patent: 4987529 (1991-01-01), Craft et al.
patent: 5485586 (1996-01-01), Brash et al.

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