1996-06-07
1998-08-18
Teska, Kevin J.
G06F 13366
Patent
active
057969680
ABSTRACT:
In a computer system where a plurality of bus masters are connected to a bus, a bus arbiter connected to the bus, comprises an arbitration circuit that arbitrates between the bus access request signals from the plurality of bus masters and outputs a bus access grant signal to a single bus master of the plurality of bus masters, unit for holding a value indicating the duration during which the switching of the bus access grant signal is to be inhibited, counting unit capable of counting on the basis of the value held in the holding unit, unit for causing the counting unit to start counting at the time when the arbitration circuit has given a bus access grant signal to a bus master, unit for inhibiting the arbitration circuit from switching the bus access grant signal in the period until the counting has been completed, as long as the bus access request signal from the bus master to which the bus access grant signal has been given remains active, and unit for permitting the arbitration circuit to switch the access grant signal after the counting has been completed.
REFERENCES:
patent: 5392436 (1995-02-01), Jansen et al.
patent: 5467295 (1995-11-01), Young et al.
patent: 5471590 (1995-11-01), Melo et al.
patent: 5506972 (1996-04-01), Heath et al.
patent: 5577214 (1996-11-01), Bhattacharya
patent: 5596729 (1997-01-01), Lester et al.
Kabushiki Kaisha Toshiba
Mohamed Ayni
Teska Kevin J.
LandOfFree
Bus arbiter used in a computer system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Bus arbiter used in a computer system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Bus arbiter used in a computer system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1124477