Bus arbiter employing a transaction grading mechanism to dynamic

Details Bus arbiter employing a transaction grading mechanism to dynamic Bus arbiter employing a transaction grading mechanism to dynamic

1996-03-26

1998-09-08

Bowler, Alyssa H.

395303, 395861, 395732, G06F 1326, G06F 1318, G06F 1334, G06F 13366

Patent

active

058058400

ABSTRACT:
A computer system includes a bus arbiter for controlling the ownership of a bus to which a variety of both real time and non-real time resources are coupled. The bus arbiter includes a request detection unit for detecting bus request signals of a plurality of bus masters, and a grant generator for generating corresponding grant signals to indicate a grant of ownership of the bus. A set of programmable registers are provided to receive configuration information for controlling the relative priority given to each of the bus masters when bus request contention occurs. One or more of the bus masters is configured to generate a grading signal following a particular bus transaction to indicate whether the latency in obtaining the bus during the previous bus request phase was generous, was acceptable, or was longer than desired (i.e., the latency requirement for the device was either violated or reached a critical or near-critical point). If the grading signal indicates the master desires faster access to the bus, the arbitration control unit increases a level of arbitration priority given to that master for future bus requests.

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