Bus allocation control apparatus

Communications: electrical – Digital comparator systems

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G06F 918

Patent

active

040178412

ABSTRACT:
A bus allocation system for a plurality of digital processing devices which are to be given access to a common data bus in a predetermined sequence. The devices include synchronized counters incremented once each time a data communication is made on the bus from any device. The counters operate through a repeating cycle of counts, and each device is enabled to communicate data during a predetermined one or more of the counts in each cycle.

REFERENCES:
patent: 3311889 (1967-03-01), Birmingham et al.
patent: 3333250 (1967-07-01), Hill et al.
patent: 3573856 (1971-04-01), Best et al.
patent: 3602889 (1971-08-01), Gayman et al.
patent: 3771135 (1973-11-01), Huettner et al.

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