Bus adapter module with improved error recovery in a multibus co

Details Bus adapter module with improved error recovery in a multibus co Bus adapter module with improved error recovery in a multibus co

1987-09-04

1989-06-06

Pellinen, A. D.

Excavating

364200, 364900, 375 7, G06F 1110

Patent

active

048377678

ABSTRACT:
A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.

REFERENCES:
patent: 4072853 (1978-02-01), Barlow et al.
patent: 4295219 (1981-10-01), Draper et al.
patent: 4661905 (1987-04-01), Bomba et al.
patent: 4692893 (1987-09-01), Casper
Shu-Shia Chow; PILA Hardware Specification; 1982; pp. 1, 5-8.

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