Burst synchronizing circuit

Details Burst synchronizing circuit Burst synchronizing circuit

1999-07-14

2003-05-20

Chin, Stephen (Department: 2634)

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

C375S368000, C370S518000, C327S152000

Reexamination Certificate

active

06567484

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a burst synchronizing circuit which synchronizes a received data signal in a burst fashion and a sampling phase of the received data signal with each other. More particularly, the present invention is concerned with a burst synchronizing circuit used in an optical subscriber transmission system, in which the received data signal is sampled by a sampling clock synchronized with a stable range of the bit position of the received data signal at the time of receiving the data signal transmitted in the burst fashion as a continuous signal.
2. Description of the Related Art
FIG. 1
is a diagram of an optical subscriber transmission system, which is an example of a system in which a data signal arranged in the burst fashion is transmitted. The optical subscriber transmission system shown in
FIG. 1
includes a master station
20
-
1
and a plurality of slave stations
20
-
2
(#
1
-#n), which are coupled with the master station
20
-
1
via optical fibers
20
-
3
and an optical coupler
20
-
4
. The slave stations
20
-
2
correspond to subscribers.
The master station
20
-
1
continuously transmits a data signal addressed to the slave stations
20
-
2
(#
1
-#n) in a down transmission direction. The data signal transmitted in the down transmission direction branches at the optical coupler
20
-
4
, and is transmitted to the slave stations
20
-
2
(#
1
-#n) in the broadcasting style. Each of the slave stations
20
-
2
(#
1
-#n) discriminates the respective address signal included the data signal transmitted in the down transmission direction, and acquires only the data signal addressed to its own station.
The slave stations
20
-
2
(#
1
-#n) transmit data signals to the master station
20
-
1
in an up transmission direction at respective timings in the burst fashion in order to prevent the data signals from colliding with each other. In this case, the data signal is continuously transmitted in the down transmission direction. Hence, each of the slave stations
20
-
2
(#
1
-#n) can perform a retiming operation on the received data signal by using a PLL (Phase-Locked Loop) circuit or the like.
In contrast, the data signals are transmitted in the up transmission direction in the burst fashion. The optical fibers
20
-
3
become longer as the slave stations
20
-
2
(#
1
-#n) are located a longer distance away from the master station
20
-
1
. Hence, the master station
20
-
1
receives the burst signals transmitted by the slave stations
20
-
2
(#
1
-#n) at different bit positions and different optical signal levels.
Hence, each time the burst data signal is received, the master station
20
-
1
is required to select, during a short time, the optimal sampling phase for latching the burst data signal with an appropriate bit phase by using a preamble signal added to the leading end of the burst data signal and to perform the retiming operation on the burst data signal.
FIG. 2
is a block diagram of a burst signal receiving part of the master station
20
-
1
. As shown, the optical burst signal received through the optical fiber
20
-
3
is converted into an electric signal by an optical module
21
-
1
. The electric signal is then subjected, by a burst synchronizing circuit
21
-
2
, to the retiming operation for latching the data bits of the electric signal with the optimal phase as described above.
Generally, the burst data signal includes a delimiter pattern added to the leading end of the burst data signal in addition to the preamble signal. The delimiter pattern which a data pattern for frame synchronization for identifying the phase of the whole burst signal. A delimiter synchronizing circuit
21
-
3
performs a delimiter synchronization using a delimiter pattern signal. A data processing part
21
-
4
processes the received data on the basis of the data signal obtained after the delimiter synchronization.
FIG. 3
is a diagram of a waveform of the output signal of the optical module
21
-
1
(which is the input signal of the burst synchronizing circuit
21
-
2
). The output signal of the optical module
21
-
1
has a pulse width which varies due to deterioration of the performance of a built-in optical amplifier and/or deterioration of the S/N ratio. More particularly, A pulse width (a one-bit cycle) T of one time slot has edge-indeterminate areas &tgr; in the rising and falling edges thereof, as illustrated by dotted areas. The remaining section of the pulse except the edge-indeterminate areas &tgr; is the valid pulse width within which the sampling can duly be performed. A parameter of how much variations in the pulse width can be tolerated is one of the indexes describing the performance of the burst synchronizing circuit.
FIG. 4
is a block diagram of the conventional burst synchronizing circuit
21
-
2
. An input data signal obtained by converting an optical signal transmitted over an optical fiber into an electric signal is sampled with a plurality of different phases with the period of one bit by a data sampling part
23
-
1
. Thus, the data sampling part
23
-
1
sequentially outputs pieces of sampled data of the input data signal having mutually different phases.
An edge detecting part
23
-
2
compares the pieces of sampled data having the neighboring phases with each other, and detects a sampling phase which causes a change of data (the rising or falling edge of the data bit waveform). Based on the detection result obtained by the edge detecting part
23
-
2
, a select signal generating part
23
-
3
generates a select signal used to select the sampled data obtained by sampling with the optimal phase, and outputs the select signal to a selector
23
-
4
. Then, the selector
23
-
4
selects the sampled data obtained by sampling with the optimal phase in accordance with the select signal, and outputs it to the next stage.
There are a variety of means, provided in the data sampling part
23
-
1
, for sampling the input data signal with a plurality of different phases with the one-bit period and sequentially outputting pieces of sampled data having the mutually different phases. For example, the input data signal is sequentially delayed at intervals shorter than the one-bit period, and delayed signals are sampled by a system clock (which is a clock having the one-bit period of the input data signal). By way of another example, the input data signal is sampled by a clock faster than the above-mentioned system clock. By way of yet another example, the system clock is sequentially delayed at intervals shorter than the one-bit period, so that multiple phase clocks are generated. Then, the input data signal is sampled by the multiple phase clocks.
There are a variety of means, provided in the edge detecting part
23
-
2
, for detecting the sampling phase which causes a change of data. For example, there is a single-side edge detecting method in which either the rising edge or the falling edge of the signal is detected from the pieces of sampled data having the mutually different phases by means of an edge pattern decoder. There is also a both-side edge detecting method in which both the rising and falling edges of the signal are detected. By way of yet another example, the positions of the edges are detected over a plurality of bit positions and are then averaged, so that the average position can be detected. This method is called a multiple-point edge detecting method.
The single-side edge detecting method detects the phase of the one-side edge of a bit in the input data signal. The above bit is a bit changed from “0” to “1”, namely, from a low level to a high level, or a bit changed from “1” to “0”, namely, from the high level to the low level. Then, the sampled data obtained by sampling using the sampling clock after a given timing passing over the section of the related edge-indeterminate area is selected from the phase position of the detected edge.
The both-side edge detecting method detects the phases of the both-sides

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