Burst SRAMS for use with a high speed clock

Details Burst SRAMS for use with a high speed clock Burst SRAMS for use with a high speed clock

1993-03-22

1997-02-18

Chan, Eddie P.

395432, 395556, 395559, G06F 1328

Patent

active

056048840

ABSTRACT:
Burst SRAMs designed for operation at a given data rate corresponding to the frequency of a first clock signal but capable of operation using a higher frequency clock signal. The burst SRAMs are preferably incorporated into the cache memory of a second level cache coupled to the processor bus in a computer system, where the computer system is preferably based on a 66-MHz P5 microprocessor. A cache controller, preferably incorporated within a memory controller, controls operation of the second level cache memory by providing the address load and address advance signals. The burst SRAMs are capable of recognizing the faster clock pulses, as well as the shorter pulses asserted on the address load and address advance signals. The address control signals are asserted and then negated during consecutive clock cycles of the faster clock signal, so that the burst SRAMs effectively operate at the same data rate corresponding to the lower frequency clock signal.

REFERENCES:
patent: 4631659 (1986-12-01), Hayn, II et al.
patent: 5134699 (1992-07-01), Aria et al.
patent: 5239639 (1993-08-01), Fisher et al.
486 Microprocessor Hardware Reference Manual, 1990.
"Improving the SRAM Interface", Electronic Engineering, vol. 63, No. 775, Jul. 191, London GB, p. 51.
"Optimum Timing Auto-Configurable Microcoded Memory Controller", IBM Technical Disclosure Bulletin, vol. 33, No. 6A, Nov. 1990, pp. 269-272.
The Motorola Semiconductor, 32K.times.9 Bit Burst Ram Synchronous Static Ram Technical Data Sheets, 1992, pp. 1-12.

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