Burst read incorporating output based redundancy

Details Burst read incorporating output based redundancy Burst read incorporating output based redundancy

2000-11-28

2001-10-23

Zarabian, Amir (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S200000

Reexamination Certificate

active

06307787

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to output based redundancy in a flash memory. Flash random access memory (RAM), more commonly known as flash memory, is a form of non-volatile storage that uses a memory cell design with a floating gate. High voltages are applied to the memory cell inputs to program or store charge on the floating gate or to erase or remove charge from the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce a thin dielectric material, reducing the amount of electronic charge on the floating gate. Erasing a cell sets the logical value of the cell to “1” while programming the cell sets the logical value to “0”. Aside from programming or erasing operations, a flash memory operates similarly to a randomly accessible read only memory (ROM). Conventionally, a flash memory chip, including the flash memory storage cells and support logic/circuitry, is made by fabricating layers of semiconductor material and interconnect layers of polysilicon and first and second metal layers onto a substrate. It will be appreciated that there are numerous integrated circuit fabrication techniques, involving more or fewer layers, which are applicable herein.
Newer technologies, such as simultaneous read and write operation flash memories, present opportunities for the redesign of CAM circuitries and architectures and their associated output circuitry to meet increasing standards of system performance, and device density. It would be desirable to implement a more efficient redundancy CAM circuitry and architecture and associated output circuitry.
Redundant core cell arrays are utilized to substitute for inoperative or defective memory core cells of primary or regular arrays. Content addressable memory (CAM) circuitry may be utilized to assist in redundancy substitution. Redundancy CAM cells store information regarding the locations of inoperative or defective memory cells so that redundant arrays of memory cells may be used to substitute for the inoperative or defective memory cells of the primary arrays.
Typically, the arrays of memory cells are tested by the manufacturer for performance and accuracy prior to utilization by a customer or user. The redundancy CAM cells are erased and programmed with the locations of inoperative memory cells as appropriate following the testing stage.
Core cells in memory may be byte or word addressable. If a particular operation is to be performed at a primary array, an address for the operation is supplied. At present, before the memory cell location for the primary array is accessed, the address is compared with address information relating to the location of the inoperative memory cells. If the address matches a location of a group of inoperative memory cells, the address is redirected to the redundant array. The operation is then performed at the redundant array. If the address does not match a location of a group of inoperative memory cells, the address is applied to the primary array, and the operation is performed at the primary array. Typically, this substitution of primary array memory cells with redundant array memory cells is seamless and transparent to the user of the memory.
Newer technologies, such as simultaneous read and write operation flash memories, present opportunities for the redesign of CAM circuitries and architectures and their associated output circuitry to meet increasing standards of system performance, and device density. The presently preferred embodiments described herein implement a more efficient redundancy CAM circuitry and architecture and associated output circuitry in a memory such as a flash memory.
A CAM cell is configured to store information regarding a location of an inoperative memory cell in a primary core cell array. Typically, the inoperative memory cell requires a substitution with a memory cell in a redundant array. The information stored in the CAM cell may relate to whether a memory cell, as addressed by an operation address of the primary core cell array requires a substitution with a memory cell of a redundant array.
Referring now to
FIG. 1
, it is a block diagram of a memory
100
according to a presently preferred embodiment. In the illustrated embodiment, the memory
100
is configured as a flash memory formed as a complementary metal-oxide-semiconductor (CMOS) integrated circuit for storing digital data. However, the memory
100
may take any other suitable form and in fact the principles described herein may be applied in any other suitable circuit in which simultaneous operation permits a dual-ported CAM architecture. The memory
100
includes a core cell array
102
, a decoder
104
, address buffer circuitry
108
, redundancy CAM circuitry
106
, a control logic circuit
110
, and sense amplifier and output circuitry
112
. The control logic circuit
110
is coupled to the decoder
104
, the address buffer circuitry
108
, and the sense amplifier and output circuitry
112
. The control logic circuit
110
produces a series of read and write select operation signals RSEL, WSEL and distributes the signals to the decoder
104
and the redundancy CAM circuitry
106
. Preferably, the control logic circuit
110
distributes timing and other control signals for the memory
100
.
The core cell array
102
includes a plurality of memory cells, each configured to store data. In some applications, each memory cell may store a single bit of data; in other applications, each memory cell may store two or more bits of data. The memory cells of the core cell array
102
may be byte or word addressable and are accessed by a corresponding address at the address buffer circuitry
108
. In one embodiment, the memory cells are accessed as data words, and the addresses correspond to unique data words. However, as will be apparent to one of skill in the art, other embodiments are possible where each memory cell has a unique address, which is decoded by the decoder
104
.
The decoder
104
typically includes row or x-address decoding logic and bit line or y-address decoding logic. The x-address decoding logic of the decoder
104
responds to an address signal ADD provided from the address buffer circuitry
108
by activating one word line of a plurality of word lines, each word line being associated with one row of the core cell array
102
. In response to activation of the word line, memory cells associated with that word line turn on and begin sinking current. To adequately turn on the memory cells, the word line must be varied by a substantial potential difference, such as 3.0 to 4.0 V, for example.
The y-address decoding logic of the decoder
104
couples the appropriate bit line of the core cell array
102
to the sense amplifier and output circuitry
112
. The y-address decoding logic responds to an address ADD from the address buffer circuitry
108
to decode the selected bit line from among a plurality of bit lines of the core cell array
102
. The sense amplifier and output circuitry
112
senses the current in the selected memory cell of the core cell array
102
and determines the binary state of the one or more bits of data stored in the selected memory cell. The circuitry
112
produces the memory cell data that are sensed, in one embodiment, as data words by the sense amplifier circuitry
112
at the output of the memory
100
for use external to the memory
100
. Other circuitry, not shown in
FIG. 1
, provides for programming, reading, verifying, erasing, and performing other operations as necessary on the individual memory cells of the core cell array
102
.
The memory
100
operates in response to a supply voltage, labeled V
cc
in FIG.
1
. The potential difference between V
cc
and ground is the supply voltage and may be in the range 0.8 to 3.3 volts, for example. The suitability of the supply voltage V
cc
will depend on a variety of factors, including the techn

Affiliated with

Also associated with

Rating

Burst read incorporating output based redundancy does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Burst read incorporating output based redundancy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Burst read incorporating output based redundancy will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2615175