Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-02-14
2006-02-14
Nguyen, Viet Q. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S230010, C365S236000, C365S239000, C365S238500, C365S230090, C365S230030
Reexamination Certificate
active
06999376
ABSTRACT:
A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data read from a group of columns during a burst operation. The burst columns are generated using an internal counter and an externally provided start address. The memory generates the burst column addresses by modifying the least significant column address signals only. For a burst length of two, only the least significant address bit is modified. For a burst length of four, only the two least significant address bits are modified. Finally, only the three least significant address bits are modified for a burst length of two. In one embodiment, the burst addresses rotate through the defined column group in a cyclical manner.
REFERENCES:
patent: 5041886 (1991-08-01), Lee
patent: 5386385 (1995-01-01), Stephens, Jr.
patent: 5537354 (1996-07-01), Mochizuki et al.
patent: 5600605 (1997-02-01), Schaefer
patent: 5666321 (1997-09-01), Schaefer
patent: 5668773 (1997-09-01), Zagar et al.
patent: 5729709 (1998-03-01), Harness
patent: 5749086 (1998-05-01), Ryan
patent: 5751039 (1998-05-01), Kauffman et al.
patent: 5787457 (1998-07-01), Miller et al.
patent: 5936903 (1999-08-01), Jeng et al.
patent: 5966724 (1999-10-01), Ryan
patent: 5974514 (1999-10-01), Andrewartha et al.
patent: 5986943 (1999-11-01), Isa
patent: 5995438 (1999-11-01), Jeng et al.
patent: 5999197 (1999-12-01), Satoh et al.
patent: 6026465 (2000-02-01), Mills et al.
patent: 6028812 (2000-02-01), Tanaka
patent: 6038196 (2000-03-01), Oh
patent: 6091665 (2000-07-01), Dorney
patent: 6108265 (2000-08-01), Takeuchi
patent: 6122718 (2000-09-01), Ito
patent: 6125078 (2000-09-01), Ooishi et al.
patent: 6137133 (2000-10-01), Kauffman et al.
patent: 6141247 (2000-10-01), Roohparvar et al.
patent: 6172935 (2001-01-01), Wright et al.
patent: 6192002 (2001-02-01), Merritt
patent: 6212596 (2001-04-01), Vogley
patent: 6229759 (2001-05-01), Morgan
patent: 6381715 (2002-04-01), Bauman et al.
patent: 6415374 (2002-07-01), Faue et al.
patent: 6473358 (2002-10-01), Noda et al.
patent: 6542422 (2003-04-01), Furutani et al.
patent: 6580659 (2003-06-01), Roohparvar
patent: 6601156 (2003-07-01), Blodgett
patent: 6665222 (2003-12-01), Wright et al.
patent: 6760274 (2004-07-01), Roohparvar
patent: 000348113 (1989-12-01), None
Keeth, et al., “DRAM circuit design: a tutorial,” IEEE Press, 2001, pp. 16-23, 142-153.
Micron Semiconductor Products, Inc., “2Mb, Smart 5 BIOS-Optimized Boot Block Flash Memory,”Flash Memorywww.micron.com, copyright 2000, Micron Technology, Inc., pp. 1-12.
Micron, “16 Mb: ×16 SDRAM”Synchronous DRAM, www.micron.com, copyright 1999 Micron Technology, Inc., pp. 1-51.
Leffert Jay & Polglaze PA
Micro)n Technology, Inc.
Nguyen Viet Q.
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