Patent
1996-09-19
1998-09-15
Bowler, Alyssa H.
395310, 395855, 395181, 39518215, 39518319, 39518509, G06F 1332, G06F 1328, G06F 1342
Patent
active
058092609
ABSTRACT:
Blocks of data are transferred in burst mode from a first device attached to a first bus, to a second device attached to a second bus having time multiplexed address/data lines. A bridge circuit includes an address register, which is coupled to the first bus, a circuit for incrementing the address register, and an output register coupled to the address/data lines of the second bus. In an aborted burst mode transfer of a block of data from one device to the other in which a "last" data byte in the block was successfully transferred, but a "next" byte of data was not successfully transferred, the system provides for an efficient retry of the transfer of the aborted data block. This efficient retry is accomplished in part by swapping the information in the address register of the bridge circuit with the information in its output register, such that the output register contains the address of the "next" data byte. After the address of the "next" data byte is placed on the second bus, a second swap occurs, such that the "next" data byte itself is moved back into the output register.
REFERENCES:
patent: 5303354 (1994-04-01), Higuchi et al.
patent: 5499346 (1996-03-01), Amini et al.
patent: 5509127 (1996-04-01), Datwyler et al.
patent: 5655076 (1997-08-01), Jimura et al.
Bowler Alyssa H.
International Business Machines Corp.
McKinley Martin J.
Rossi Jeffrey Allen
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