Burst frame phase synchronizing circuit and burst frame phase sy

Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal

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370512, H04J 306

Patent

active

059636050

ABSTRACT:
A burst frame phase synchronizing circuit is disclosed, whereby the generation of erroneous synchronization caused by the phase fluctuation of received data or a bit error is prevented. A transmission error monitoring circuit 15 monitors a transmission error and outputs error information, and a transmission error statistical circuit 14 outputs protection information obtained by summing up the statistics of transmission errors. A frame synchronizing pattern comparator circuit 11 makes a comparison for bit strings between burst data at the time of transmission and a specified synchronizing pattern and outputs comparison information obtained based on the production state of a noncoincidence bit. A synchronization protective circuit 13 selects a permissible noncoincidence bit number and outputs a frame synchronizing signal satisfying a specified protection condition. Thus, since the strength of synchronization protection is flexibly switched according to a transmission line error, a synchronous bit length can be controlled without taking any unnecessarily strong synchronization protecting measures, and transmission efficiency can be improved by controlling a frame synchronous bit length.

REFERENCES:
patent: 4414676 (1983-11-01), Kraul et al.
patent: 4675722 (1987-06-01), Hackett
patent: 5570370 (1996-10-01), Lin
patent: 5592518 (1997-01-01), Davis et al.

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