Burst error correction using cyclic block codes

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371 2, G06F 1110

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active

044883021

ABSTRACT:
Methodology, and associated circuitry, for encoding and decoding data words to provide burst error correction capability are disclosed.
Encoder (14): partitions the data words into a plurality of subrate streams; individually codes these streams utilizing a block coding technique; and then recollates the coded streams as well as the associated parity words in an interleaved order to produce the encoder output.
Decoder (20): partitions the received words into a corresponding plurality of subrate received streams; individually computes the syndrome as well as shifted and divided versions of the syndrome for each received stream; after each shift and divide, compares the partial remainder with the applicable code characteristic polynomial; and corrects the applicable bit in the corresponding received subrate stream whenever the comparison indicates an error has occurred.

REFERENCES:
patent: 3582881 (1971-06-01), Burton
patent: 3585586 (1971-06-01), Harmon
patent: 4238852 (1980-12-01), Iga et al.
patent: 4312069 (1982-01-01), Ahamed
patent: 4398292 (1983-08-01), Doi et al.
patent: 4400810 (1983-08-01), Ive
patent: 4413340 (1983-11-01), Odaka
patent: 4425644 (1984-01-01), Scholz
Franco, Coding for Error-Free Communications, Electro-Technology, Jan. 1968, pp. 53-62, excl. 54.

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