Excavating
Patent
1989-11-13
1991-09-17
Beausoliel, Robert W.
Excavating
371 391, G06F 1110
Patent
active
050501712
DESCRIPTION:
BRIEF SUMMARY
DESCRIPTION
1. Technical Field
This invention relates to a burst error correction apparatus suitable for correcting burst error due to a bit slip in a self-clocking signal containing resync codes at predetermined intervals, e.g., a self-clocking signal read out from, for example, a digital recording medium before this signal is demodulated.
2. Background Art
Conventionally, as is well-known, digital data to be recorded on a magnetic or optical recording medium is converted into or modulated to a signal form suitable for recording/reproduction of the digital data.
There are typical examples of system applied to this modulation: MFM (modified frequency modulation) system; 2.7 RLL (run length limited code) system; and EFM (eight to four-teen modulation) system. All signals modulated by these modulation systems are signals in which data bits and clock bits are basically indistinguishable from each other and which are codes which generate clock on the basis of their own data. That is, they are self-clocking signals. These codes are in common with each other in the following respects. The number of bits after the modulation (channel bits) is larger than that before the modulation, and the formation of any succession of "1" is avoided. The number of "0" between "1"s is called run length (RL). For example, the RL varies as circuit for the reproduction of clock becomes difficult. If the RL is excessively short, interbit interference becomes large.
FIG. 10 shows an example of modulation of data 9 Ah (h designates hexadecimal) based on the MFM system. That is, 1-byte data "10011010" is converted into channel bits of 2-byte channel bits "0100 1001 0100 0100" on the basis of the principle of this system.
FIG. 11 shows a table of conversion correspondence in the case of the 2.7 RRL system, and FIG. 12 shows an example of modulation of data 9 Ah (h designates hexadecimal) based on the 2.7 RRL system. It is understood that in this example 1-byte data "10011010" is converted into 2-byte channel bits "0100 0010 0010 0100" in accordance with the relationship shown in FIG. 11.
For reproduction of original data from such a self-clocking signal, a PLL circuit or the like is ordinarily used to generate clock on the side of the reader. There is a possibility of a temporary disturbance of the clock timing under the influence of something (e.g., scratch on the recording medium) such that, after the occurrence of disturbance, data is read out by the timing shifted by 1 to several bits. This phenomenon is called bit slip. In such a case, the data subsequent to the point at which the clock timing is temporarily disturbed (bit slip occurrence point) is generally all treated as error (burst error due to bit slip) because the data partitions are shifted.
A conventional method of limiting the length of this burst error is known in which a specific pattern for effecting resynchronization (i.e., resync code) is previously written at a predetermined position, whether or not this resync code is located at the predetermined position is determined during reading, and, in a case where it is located within a range of several bits before and behind the predetermined position but is not located right at this position, the occurrence of a bit slip is recognized, thereby enabling the data subsequent to the resync code to be read correctly.
There have been proposed formats using this type of resync code, e.g., ISO-DIS 9171-1, ISO-DIS 9171-2 for post-write type of optical disks, as described on pp 75 to 76 of NIKKEI ELECTRONICS, 1987, 11.2 (No. 433).
FIG. 13 shows a schematic diagram of a data field of a post-write type of optical disk for processing with 2.7 RLL modulation. In FIG. 13, SYNC represents 3-byte data for synchronization, D0 to D1023 represent user data of 1024 bytes, CD0 to CD11 represent control data, CRC represents 4-byte user CRC data, P0,0 to P9,15 represents parity codes of 160 bytes (read solomon code (LDS-RS)), and R represents 1-byte resync code (hereinafter referred to simply as resync), each 1 byte being placed every 20 bytes.
REFERENCES:
patent: 3893171 (1975-07-01), Marshall
patent: 3938086 (1976-02-01), Valbonesi
patent: 4959834 (1990-09-01), Aikawa
patent: 4975916 (1990-12-01), Miracle
Beausoliel Robert W.
Fogiel Max
Kabushiki Kaisha CSK
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