Burst-error correcting system

Details Burst-error correcting system Burst-error correcting system

1983-05-06

1984-09-11

Atkinson, Charles E.

Excavating

371 2, 371 43, G06F 1110

Patent

active

RE0316660

ABSTRACT:
In a digital signal transmission system, a predetermined number of words of digital information signals are added bit by bit in a modulo 2 adder to produce a first parity signal. The information signals and the first parity signal are delayed so as to have different delay times to each other, and the signals thus delayed are again added bit by bit in a modulo-2 adder to produce a second parity signal. The predetermined number of words of information signals and first and second parity signals are serially transmitted through a transmission line.

REFERENCES:
patent: 3409875 (1968-11-01), De Jager et al.
patent: 3538497 (1970-11-01), Harmon
patent: 3605090 (1971-09-01), Burton
patent: 3882457 (1975-05-01), En
patent: 4032886 (1977-06-01), En et al.
patent: 4044328 (1977-08-01), Herff

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