Pulse or digital communications – Receivers – Automatic baseline or threshold adjustment
Reexamination Certificate
1998-02-12
2001-10-02
Luther, William (Department: 2664)
Pulse or digital communications
Receivers
Automatic baseline or threshold adjustment
C375S340000
Reexamination Certificate
active
06298098
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to data transmission systems, and more particularly the invention relates to a burst demodulator for use in a high speed bidirectional digital transmission of voice, video, and data.
Much attention is being directed to converting any directional analog data transmission systems, such as the community antenna television (CATV) cable system into a more versatile bidirectional communication system. Today, over 60 million households in the United States enjoy the benefits of cable TV, virtually all of the information which travels into the home over the cable is in the form of analog television signals. Some subscribers now have the ability to send digital signals to select movies or provide other forms of low rate data information from the home to a central location. However, in the next few years the rate of digital information both entering and leaving the home over the CATV cable will increase dramatically. Equally, hybrid fiber/coax (HFC) plants are being installed for telephone/data outside the present CATV systems.
Disclosed in U.S. Pat. No. 5,553,064 by Paff et al. is a cable data transmission system which utilizes time division multiplexing in a downstream direction from a headend unit to multiple subscribers and a time division multiple access transmission from subscribers to the headend unit. The multiple upstream and downstream data channels are shared using different frequency bands. In the downstream, data are broadcast to all subscribers. However, each subscriber is assigned an identification number and a specific carrier frequency for receiving data. The bitstream is continuous using time division multiplexing (TDM) and frequency division duplex (FDD). In the upstream, subscribers send data to the headend in a burst fashion in assigned time slots using time division multiple access (TDMA). A quadrature phase shift keyed (QPSK) modulator is provided for data encoding and modulation for upstream and downstream transmission. In accordance with a feature of the invention claimed therein, a headend burst demodulator is provided for receiving data at the headend from subscribers. A Barker code is utilized in a preamble for data acquisition and synchronization of the data.
The present invention is directed to an improved data preamble and headend demodulator for use therewith which achieve closer spacing of data bursts along with burst acquisition and synchronization.
SUMMARY OF THE INVENTION
In accordance with the invention, a data burst is preceded by a preamble which is a repeating pattern of ones (1) and zeros (0) which is simple to detect and provides a high signal-to-noise ratio at the output of a detector. The repeating pattern is utilized to detect burst signal presence and to measure symbol clock phase without the need for time tracking loop in the demodulator thus reducing demodulator complexity.
In a preferred embodiment, a 14 symbol BPSK preamble has the format 10101010101000. The last three symbols are designed to contrast with the repeating pattern established by the first 12 symbols. The contrasting pattern, when detected, results in the establishment of frame synch.
A feature of the invention is the use of an empty “burst” during which no subscriber transmits, which allows the demodulator to measure background noise power and set an acquisition threshold based on the average noise measurement. This greatly improves the dynamic range of the demodulator.
Another feature of the invention is the use of a first in—first out (FIFO) memory in the demodulator which allows the data bursts to be closely spaced in time. Since the burst demodulator utilizes pipelining in concurrently operating on successive data bursts, which might have different clock phases, the FIFO allows asynchronous input and output clocks.
REFERENCES:
patent: 5553064 (1996-09-01), Paff et al.
patent: 5561469 (1996-10-01), Schultz
Currivan Bruce J.
Edwards Allen Ponsford
Krasner Norman F.
Xenakis William G.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Luther William
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