Burst address sequence generator

Details Burst address sequence generator Burst address sequence generator

1991-04-22

1994-06-07

Dixon, Joseph L.

Static information storage and retrieval

Magnetic bubbles

Guide structure

365194, 36523002, 36523008, 365236, G06F 1200, G11C 800

Patent

active

053197593

ABSTRACT:
A burst address sequence generator generates a sequence comprised of 2.sup.n addresses (where n is an integer greater than 1) which are compatible with an INTEL 80486 CPU burst order. A first embodiment of the burst address sequence generator latches an initial address, and uses a binary up counter and exclusive or (XOR) logic to generate the sequence of addresses. A second embodiment of the burst address sequence generator requires a shorter delay time to generate the addresses, and is comprised of a delay unit, an inverter, a counter, and a programmable logic device, such as a PAL or a PLD. Both embodiments are adaptable for use with a dynamic random access memory (DRAM). The design of each embodiment is readily applicable to generate the sequence of addresses necessary to transmit 2.sup.n data units of 2.sup.m bytes per unit, where both m and n are integers greater than 1.

REFERENCES:
patent: 5126975 (1992-06-01), Handy et al.

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