Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-12-29
2002-11-05
Tran, M. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S230060
Reexamination Certificate
active
06477082
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to memory devices with burst read access.
BACKGROUND OF THE INVENTION
Integrated circuit memory devices are available in numerous configurations. For example, volatile and non-volatile memory devices are commonly implemented. In addition, numerous methods of reading and writing to memory devices are known to those skilled in the art.
Random access memory devices have memory cells that are typically arranged in rows and columns. During operation, a row (page) is accessed and then memory cells can be randomly accessed on the page by providing column addresses. This access mode is referred to as page mode access. To read or write to multiple column locations on a page requires the external application of multiple column addresses. To increase access time, a burst mode access has been implemented. The burst mode uses an internal column address counter circuit to generate additional column addresses. The address counter begins at an externally provided address and advances in response to an external clock signal (synchronous memory) or a column address strobe signal (non-synchronous memory).
Different architectures of memory devices have also been implemented to decrease the time period between output data. One architecture uses multiple array segments. Each array segment is used to read a memory column(s) simultaneously. Data from one of the memory segments is then selected for output. The remaining segments can then be output sequentially in response to subsequent clock cycles.
In operation, a common row address for the memory segments is accessed. In addition, a common column address is used to select a column from each segment. It will be appreciated that the memory array can be viewed as three-dimensional. That is, each segment can be X-bits deep to provide a data word having length-X in response to a single row and column address. The above architecture allows for fast output of data from the selected column of each array segment. However, when different column data is required from some of the segments, a clock Wait state is required. That is, the memory needs time to access and read data from a different memory array column. Each column address in the array segments defines a page boundary. For example, in a memory device having four array segments, a page boundary is encountered every four data word, see FIG.
1
. In
FIG. 1
, data locations
0
,
1
,
2
and
3
are located in four different segments but have the same column address in each segment (column address A
1
). Likewise, data locations
4
,
5
,
6
and
7
are located in the four different segments but have the same column address in each segment (column address A
2
). Thus, to read data words
2
,
3
,
4
and
5
a page boundary must be crossed and the column address incremented.
FIG. 2
, illustrates the output of data words
2
,
3
,
4
and
5
. Note that a wait state is required between data words
3
and
4
. Likewise, a linear burst output that crosses rows requires additional wait states as illustrated in FIG.
3
.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to reduce wait states in burst mode accesses in a memory device.
SUMMARY OF THE INVENTION
The above-mentioned problems with memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises a memory array with a plurality of array partitions, a first address circuit, a second address circuit, and a control circuit to independently couple either the first address circuit or the second address circuit to each of the plurality of array partitions.
In another embodiment, a memory device comprises, a memory array with a plurality of divisions, a row address circuit, a first column address circuit to provide a first address output, a second column address circuit to provide a second address output, a plurality of column decode circuits, and a control circuit to selectively couple either the first column address circuit or the second column address circuit to the individual column decode circuits.
A method for accessing a partitioned memory array comprises acquiring a first memory address, generating a second memory address, determining an address that is required by each of the individual memory array partitions, and coupling either the first memory address or the second memory address to the individual memory array segments.
Another method for accessing a partitioned memory array comprises acquiring a row address, acquiring a first column address, generating a second column address, and selectively coupling the first column address or the second column address to the individual memory array partitions.
In an additional embodiment, a memory system comprises an external processor, and a non-volatile memory coupled to the external processor. The non-volatile memory comprises, a memory array with a plurality of segments, a row address circuit, a first column address circuit to provide a first address output, a second column address circuit to provide a second address output, a plurality of column decode circuits, and a control circuit to selectively couple either the first column address circuit or the second column address circuit to the individual column decode circuits.
In yet another embodiment, a memory device comprises a memory array with a plurality of segments, a row address circuit, a first column address circuit to provide a first address output, a second column address circuit to provide a second address output, and a plurality of column decode circuits, wherein the first address output is coupled to at least one of the plurality of column decode circuits and the second address output is coupled the remainder of the column decode circuits.
In a further embodiment, a non-volatile memory device comprises a memory array with a plurality of segments, a column decode circuit coupled to a plurality of bit lines of the memory array, an address decode circuit to receive an external column address, a column address counter circuit to provide an internal column address, and a multiplexer circuit to receive outputs from both the address decode circuit and the column address counter circuit, wherein the output of the multiplexer circuit is coupled to the column decode circuit, and where the multiplexer is controlled in response to an externally provided segment starting address.
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Gualandri Stephen J.
Pekny Theodore T.
Fogg Slifer Polglaze Leffert & Jay P.A.
Micro)n Technology, Inc.
Tran M.
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