Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1999-05-11
2002-06-11
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S760020
Reexamination Certificate
active
06404219
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a burn-in test method for a semiconductor chip, a burn-in test apparatus, and a semiconductor chip to be used in a burn-in test method.
2. Description of Related Art
The burn-in test of a semiconductor chip is an accelerated life test for screening semiconductor chips having an initial failure or semiconductor chips that are out of the distribution range of a variation in the quality of manufacture by applying, to semiconductor chips, higher voltage, higher temperature stress than in actual use conditions.
In a conventional burn-in test method, first, after a wafer test, non-defective devices are subjected to assembling and rendered in a package-level state in which each device is sealed in a ceramic package or a plastic package. Then, a burn-in test is performed in such a manner that in a thermostatic chamber a number of chips are placed on a burn-in board and burn-in stress is imposed on those chips en bloc. There is another type of burn-in test method that is performed in a wafer-level state. In this burn-in test method, stress is imposed on non-defective devices in a wafer state, that is, before being subjected to assembling and sealed in a package.
FIG. 11
shows a conventional burn-in test apparatus. In
FIG. 11
, reference numeral
1
denotes a burn-in apparatus having a signal input device
20
and a DC power supply device
21
;
2
, a prober;
3
, a wafer to be mounted on a hot chuck (not shown) of the prober
2
;
10
, semiconductor chips formed on the wafer
3
;
6
, a probe card to be connected to the semiconductor chips
10
;
4
, a thermostatic chamber;
5
, a burn-in circuit board provided in the thermostatic chamber
4
; and
7
, power/signal lines that connect the burn-in apparatus
1
to the prober
2
and the burn-in circuit board
5
. In this specification, the entire apparatus constituted of the burn-in apparatus
1
, the prober
2
, the thermostatic chamber
4
, and the power/signal lines
7
is called a burn-in test apparatus.
A wafer burn-in test is performed by supplying power supply voltages and a signal from the burn-in apparatus
1
to the semiconductor chips
10
on the wafer
3
via the power/signal lines
7
that are connected to the probe card
6
. A package burn-in test is performed in such a manner that the semiconductor chips
10
are mounted on the burn-in circuit board
5
and power supply voltages and a signal are supplied via the power/signal lines
7
.
FIG. 12
is a circuit diagram of a DRAM memory cell circuit. As shown in
FIG. 12
, each DRAM memory cell is composed of a word line WL
1
or the like, a bit line BL
1
or the like, a switching transistor T
1
or the like, and a memory capacitor C
1
or the like.
FIG. 13
is an example time chart showing waveforms of burn-in stress to be imposed on the DRAM memory cell circuit of FIG.
12
. As shown in
FIG. 13
, the potentials of the word lines WL
1
-WL
4
are caused to rise one by one in order, whereby stress is imposed on the gate oxide films etc. of the switching transistors T
1
etc.
FIG. 14
is an example time chart showing waveforms of burn-in stress for causing the potentials of the word lines WL
1
-WL
4
to rise collectively to shorten the evaluation time of a wafer burn-in test. As shown in
FIG. 14
, the degree of acceleration of an accelerated life test can be made higher by increasing the memory cell selection ratio by increasing the number of switching transistors T
1
etc. on which stress can be imposed. The selection ratio means the number of selected memory cells per unit time.
However, random logic devices have a problem that because of a large memory cell selection ratio in an actual operation state, a high degree of acceleration is not expected even if the memory cell selection ratio is increased, unlike the case of memory devices such as the above-described memory cell circuit.
In logic devices whose operation speeds are now being increased, it is necessary to reinforce screening of current -mode failures in addition to voltage-mode failures. Current stress is imposed in the form of a charge/discharge current when a signal changes from “H” to “L” or from “L” to “H.” However, since burn-in test vectors are restricted in the kinds of input patterns and expected value patterns, it is difficult to perform a burn-in test by using a test pattern that enables a charge/discharge operation in every circuit. Therefore, in a burn-in test, a charge/discharge operation occurs only in part of the circuits and there are circuits on which current stress is not imposed. This results in a problem that the burn-in efficiency is not sufficiently high.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems in the art, and an object of the invention is therefore to provide a burn-in test method and apparatus and a semiconductor chip to be used in a burn-in test method that allow current stress to be imposed on every circuit node by varying a power supply voltage in pulse form, and thereby enables an efficient burn-in test.
According to a first aspect of the present invention, there is provided a burn-in test method for a semiconductor chip, comprising: a pulse voltage supplying step of supplying an inverter circuit in a semiconductor chip with a pulse voltage that is output from a pulsed power supply device and varies in a range from 0 V to a burn-in voltage; a charge/discharge step of charging a load capacitor of an internal circuit of the semiconductor chip by using the pulse voltage if an input signal supplied to the semiconductor chip is at the burn-in voltage, and discharging the load capacitor by using the pulse voltage if the input signal is at 0 V; and a step of imposing current stress on the internal circuit by using a current generated in the charge/discharge step.
According to a second aspect of the present invention, there is provided a burn-in test apparatus comprising: a burn-in apparatus having a pulsed power supply device for supplying a pulse voltage that varies in pulse form in a range from 0 V to a burn-in voltage; and a semiconductor chip that is supplied with the pulse voltage from the pulsed power supply device, wherein the semiconductor chip has an internal circuit and a load capacitor in the internal circuit, the internal circuit being given current stress in such a manner that a current is caused to flow through the internal circuit by charging the load capacitor when an input signal supplied to the semiconductor chip is at the burn-in voltage, and discharging the load capacitor when the input signal is at 0V.
According to a third aspect of the present invention, there is provided a burn-in test apparatus comprising: a burn-in apparatus having: a plurality of DC power supply devices for supplying respective DC voltages; and a burn-in control signal generation device for generating a burn-in control signal to be used for selecting one of the DC power supply devices; and a semiconductor chip that is supplied with the DC voltages from the respective DC power supply devices, the semiconductor chip having: a plurality of pulsed power supply devices for supplying respective pulse voltages that vary in pulse form in a range from 0 V to a burn-in voltage; an addition section for generating a plurality of pulse supply voltages by adding the DC voltages to the pulse voltages, respectively; a selection circuit for selecting one of the pulse supply voltages generated by the addition section in accordance with the burn-in control signal; and an internal circuit including a load capacitor, wherein the internal circuit being given current stress in such a manner that a current is caused to flow through the internal circuit by charging the load capacitor by using the selected pulse supply voltage when an input signal supplied to the semiconductor chip is at the burn-in voltage, and discharging the load capacitor by using the pulse supply voltage when the input signal is at 0 V.
According to a fourth aspect of the present invention, there is provided a burn-in te
Karlsen Ernest
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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