Burn-in stress test mode

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

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Details

324763, G01R 3128

Patent

active

060377925

ABSTRACT:
An integrated circuit structure and method provides a burn-in stress test mode that facilitates stress testing of an integrated circuit device in a burn-in oven. The integrated circuit structure and method is capable of disabling a time-out feature of an IC memory device during a stress test mode of the device in order to facilitate stress testing of the device in a burn-in oven. The integrated circuit structure provides for entry into the burn-in stress test mode when a supply voltage supplied to the integrated circuit device exceeds a predetermined voltage level and/or the temperature of the integrated circuit device exceeds a predetermined temperature level.

REFERENCES:
patent: 5068599 (1991-11-01), Niehaus
patent: 5349290 (1994-09-01), Yamada
patent: 5656944 (1997-08-01), Choi
patent: 5745499 (1998-04-01), Ong

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