Burn-in signal pattern generator

Details Burn-in signal pattern generator Burn-in signal pattern generator

1996-12-02

1999-02-16

Beausoliel, Jr., Robert W.

Excavating

39542107, G01R 3128

Patent

active

058727973

ABSTRACT:
Hardware tester and burn-in tools are emulated by providing a user-specified nested sequence of counters, logical combination of the counter outputs and generation of corresponding vectors for application to exercise an integrated circuit device. The vectors are generated in accordance with user-specified parameters and stored in static random access memory until called for application to the integrated circuit. The parameters, preferably specified through use of a graphic user interface, provide an extremely compressed representation of the vectors themselves. Provision is made to accommodate any of a plurality of waveform conventions directly in the vector. An interface table is preferably used to arbitrarily allocate bits of the vector to pins of the integrated circuit device and any of a plurality of clock signals and phases can be provided to any pin. Sequences of vectors may also be generated for each combination of counter output states in accordance with desired memory functions.

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"Algorithmic Pattern Generation at the Tester"; IBM Technical Disclosure Bulletin, vol. 32, No. 6A; Nov. 1989; N. N. Ngo et al.; pp. 76-79.

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