Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2001-03-22
2002-04-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
C324S760020
Reexamination Certificate
active
06372528
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a burn-in method and device for carrying out a reliability test of a semiconductor device, and more particularly to a wafer level burn-in method and device for carrying out a test in a state of a wafer.
2. Description of the Background Art
A burn-in test of the semiconductor device is an acceleration test for applying, to the semiconductor device, a higher voltage stress or a higher temperature stress than that in the case in which the semiconductor device is actually used as a product and for evaluating an electrical characteristic of the semiconductor device after the application of the stress, thereby screening the semiconductor device generating initial failures or the semiconductor device having the characteristic keeping away from a normal distribution.
Conventionally, a wafer test has been carried out, a non-defective chip passing the wafer test has been assembled and the burn-in test of the semiconductor device has been executed in a package condition in which the assembly is sealed with a package (a package such as a resin, ceramic or plastics). More specifically, a large number of packaged semiconductor devices are provided on a burn-in board and a burn-in stress is collectively applied in a thermostat. Thus, the electrical characteristic of each semiconductor device is evaluated after the application of the stress.
FIG. 19
is a flow chart for explaining a conventional burn-in method. First of all, a high temperature stress and an electric stress are applied to a wafer to be an evaluation object (Step SP
101
). More specifically, the electric stress is applied in a state in which the wafer is put in a high temperature furnace or the electric stress is externally applied in a state in which the wafer is mounted on a high temperature chuck.
Next, it is decided whether a predetermined stress is applied to the wafer or not (Step SP
102
). At the Step SP
102
, if it is decided that the predetermined stress is not applied to the wafer, the processing returns to the Step SP
101
where the high temperature stress and the electric stress are applied again.
On the other hand, if it is decided that the predetermined stress is applied to the wafer at the Step SP
102
, it is decided whether a defective portion is generated in each chip of the wafer or not (PASS/FAIL decision) (Step SP
103
). Furthermore, if a failure is generated, the defective portion is identified.
As a result of the PASS/FAIL decision at the Step SP
103
, it is decided whether a defective portion is to be repaired or not for a chip which is decided to have a failure generated thereon (Step SP
104
). If a result of the decision at the Step SP
104
is “YES”, the defective portion is repaired (Step SP
105
).
A chip decided as “PASS” at the Step SP
103
and a chip repaired at the Step SP
105
are subjected to an assembling step and a packaging step and are then shipped as products. On the other hand, a chip decided as “NO” at the Step SP
104
(that is, a chip which generates a failure and cannot be repaired) is not subjected to the assembling step and the like and is treated as a defective chip.
FIG. 20
is a top view typically showing a structure of a semiconductor memory to be an evaluation object of burn-in. A chip
101
has a plurality of memory cell array portions
102
, a peripheral circuit portion
103
and a logic circuit portion
104
. Each memory cell array portion
102
is provided with a plurality of memory cells arranged in a matrix, a plurality of word lines for each row of the memory cell array and a plurality of bit lines for each column of the memory cell array. A peripheral circuit such as a sense amplifier is formed in the peripheral circuit portion
103
together with a plurality of wirings. A random logic circuit is formed in the logic circuit portion
104
together with a plurality of wirings.
As a method of efficiently carrying out the burn-in by using the semiconductor memory as an object, there have been proposed a method of selecting all bit lines and all word lines at the same time and collectively applying an electrical stress to all memory cells (Japanese Patent Application Laid-Open No. 5-144910 (1993)) and a method of selecting all bit lines and half of word lines at the same time and collectively applying an electrical stress to memory cells (half of all the memory cells) connected to the word lines (Japanese Patent Application Laid-Open No. 4-756 (1992)). In such a method, a selectivity of the word line in the memory cell array portion
102
is more enhanced than that in an actual usage state. As compared with the case in which the word lines are selected one by one to carry out the burn-in as in the actual usage state, a time required for the burn-in can be shortened. In other words, the burn-in can be accelerated.
Referring to the wiring of the peripheral circuit portion
103
and the wiring of the logic circuit portion
104
, however, there is a portion where all the wirings cannot be collectively selected electrically in respect of a structure. In the conventional burn-in method, therefore, there has been a problem in that it is hard to accelerate the burn-in in the peripheral circuit portion
103
and the logic circuit portion
104
. In the conventional burn-in method in which only a high temperature stress and an electric stress are applied, particularly, a large number of test patterns of the electric stress are required for applying the electric stress to whole wirings of the logic circuit portion
104
. Therefore, there has been a problem in that the burn-in cannot be accelerated in fact.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a burn-in method comprising the steps of (a) applying one of a high temperature stress and a low temperature stress to an evaluation object, (b) applying an electric stress and the other of the high temperature stress and the low temperature stress to the evaluation object, and (c) deciding whether a failure is generated on the evaluation object or not after the steps (a) and (b).
A second aspect of the present invention is directed to the burn-in method according to the first aspect, wherein the steps (a) and (b) are executed repetitively.
A third aspect of the present invention is directed to a burn-in device comprising one of a high temperature generating portion and a low temperature generating portion which has mounting surface where an evaluation object is to be mounted, the other of the high temperature generating portion and the low temperature generating portion which is provided opposite to the mounting surface of the one of the high temperature generating portion and the low temperature generating portion and can be moved relatively to the one of the high temperature generating portion and the low temperature generating portion, an electric stress applying portion for applying an electric stress to the evaluation object, and an evaluating portion for deciding whether a failure is generated on the evaluation object or not.
A fourth aspect of the present invention is directed to the burn-in device according to the third aspect, wherein the other of the high temperature generating portion and the low temperature generating portion is provided with a plurality of through holes penetrating from one main surface opposed to the mounting surface to the other main surface.
A fifth aspect of the present invention is directed to the burn-in device according to the third aspect, wherein the other of the high temperature generating portion and the low temperature generating portion partially applies a temperature stress to the evaluation object.
A sixth aspect of the present invention is directed to the burn-in device according to any one of the third to fifth aspects, further comprising a driving mechanism for driving at least one of the high temperature generating portion and the low temperature generating portion, and a control portion for controlling the driving mechanism.
A seventh aspect of the present invention is dir
Mitsubishi Denki & Kabushiki Kaisha
Niebling John F.
Stevenson André C
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