Burn-in and test method of semiconductor wafers and burn-in boar

Details Burn-in and test method of semiconductor wafers and burn-in boar Burn-in and test method of semiconductor wafers and burn-in boar

1995-02-22

1996-07-09

Nguyen, Vinh P.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324765, G01R 3128

Patent

active

055347860

ABSTRACT:
Disclosed is an improved burn-in and test method of semiconductor wafers each having numerous integrated circuits formed therein. It includes the steps of dividing each semiconductor wafer into blocks each including some integrated circuits; giving each block an address to indicate in which part of the semiconductor wafer the integrated circuits of the block are placed; recording the addresses of all blocks; preparing burn-in boards each having sockets to detachably hold carriers each bearing an identification code; loading each carrier with a block to be tested; fitting each carrier in a selected socket in the burn-in board; and carrying out the burn-in and required tests on the blocks of each burn-in board. Analysis of test results permits the locating of defective integrated circuits, if any in semiconductor wafers in terms of the recorded addresses of the blocks and the identification codes of the carriers.

REFERENCES:
patent: 4902969 (1990-02-01), Gussman
patent: 5003251 (1991-03-01), Fuoco
patent: 5012187 (1991-04-01), Littlebury
patent: 5021733 (1991-06-01), Ebihara et al.
patent: 5289113 (1994-02-01), Meaney et al.
patent: 5414370 (1995-05-01), Hashinaga et al.

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