Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead
Reexamination Certificate
1999-05-21
2001-06-12
Quach, T. N. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
C257S506000, C438S423000
Reexamination Certificate
active
06246116
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a semiconductor integrated circuit (IC) structure, and more particularly to a buried wiring line structure.
2. Description of the Related Art
Polysilicon is usually used as a conductive material for fabricating structures in semiconductor devices such as gate electrodes and bit lines. When the size of the semiconductor device arrives at the deep submicron level, the requirement for a high operating rate creates some device stability problems.
A conventional method for forming a polysilicon wiring line is to deposit a polysilicon layer on a provided substrate by low pressure chemical vapor deposition (LPCVD). A part of the polysilicon layer is etched until the substrate is exposed. The remaining polysilicon layer is thus used as a gate electrode or a bit line. However, the step of etching the polysilicon layer has some disadvantages; for example, the etching process is complicated and the polysilicon layer formed on the substrate occupies layout space. Furthermore, polysilicon grain size, which is affected by thermal processes, affects the resistance of the polysilicon layer. If the resistance of the polysilicon line cannot be controlled accurately, the quality of semiconductor devices thus fluctuates.
Moreover, an etching process is performed to remove a part of the polysilicon layer while forming the polysilicon line. If the polysilicon layer is not removed completely, polysilicon remaining on the substrate may cause unintended connections. If the polysilicon layer is over-etched, the substrate may be damaged, which can cause defects.
A conventional buried bit line is developed to resolve the problems described above. The method of forming the buried bit line comprises the step of implanting a dopant into a substrate. However, the dopant in the substrate easily diffuses due to thermal processes after forming the buried bit line so that the distribution of the dopant cannot be controlled. Resistance of the buried bit line is thus unstable.
SUMMARY OF THE INVENTION
The invention provides a buried wiring line comprising a doped region in a provided substrate and a silicon nitride region formed around the doped region in the substrate. The doped region is used as the buried wiring line. The silicon nitride region isolates the buried wiring line from the substrate.
Forming the buried wiring line comprises steps of implanting a conductive dopant into a provided substrate to form a first silicon nitride layer using a nitric gas source. A conductive doped region is formed in the substrate above the first silicon nitride layer. A second silicon nitride layer is formed in the substrate beside the conductive doped region. The first silicon nitride layer and the second silicon nitride constitute a silicon nitride region around the conductive doped region so that the conductive doped region is isolated from the substrate.
REFERENCES:
patent: 3663308 (1972-05-01), Davey
patent: 3897274 (1975-07-01), Stehlin et al.
patent: 4939567 (1990-07-01), Kenney
patent: 5962908 (1999-10-01), Beasom et al.
patent: 6074929 (2000-06-01), Thomas
patent: 55-138267 (1980-10-01), None
Martine Penilla & Kim LLP
Quach T. N.
United Microelectronics Corp.
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