Patent
1978-07-03
1980-05-13
Edlow, Martin H.
357 23, 357 20, H01L 2978
Patent
active
042031257
ABSTRACT:
An MOS random access memory cell using the capacitance of a buried P-N junction as the storage element is formed by a process compatable with standard N-channel silicon gate manufacturing methods. The cell is fabricated using a method which consists of an implanted channel stopper underneath a thick field oxide, a buried, fully implanted charge storage element which also is the source of the cell transistor, self-aligned polysilicon gates, multilayer oxide and a thin film of metallization for interconnections. The vertical stacking of the charge storage and transfer elements and the increase in storage area to cell area ratio with the buried storage area provide a cell with very high packing density.
REFERENCES:
patent: 3748187 (1973-07-01), Aubuchon
patent: 4065783 (1977-12-01), Ouyang
Chatterjee Pallab K.
Fu Horng-Sen
Tasch, Jr. Al F.
Taylor Geoff W.
Donaldson Richard L.
Edlow Martin H.
Hiller William E.
Texas Instruments Incorporated
Williamson Ronald A.
LandOfFree
Buried storage punch through dynamic ram cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Buried storage punch through dynamic ram cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Buried storage punch through dynamic ram cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-932493