Buried layer substrate isolation in integrated circuits

Details Buried layer substrate isolation in integrated circuits Buried layer substrate isolation in integrated circuits

2001-05-04

2004-12-14

Wilczewski, Mary (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S504000, C257S509000

Reexamination Certificate

active

06831346

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit manufacturing, and more particularly to a substrate-isolated transistor and method for forming same.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Mixed signal, or mixed mode, integrated circuits which include analog and digital circuit portions are becoming increasingly popular. For example, many wireless communications applications involve mixed signal integrated circuits. Noise problems can arise in such circuits because analog circuit portions tend to be noise-sensitive, while relatively high-power switching transistors, such as output transistors associated with the digital circuit portions, tend to generate noise. In a mixed signal circuit, noise from an output transistor can be coupled to an analog circuit portion through the semiconductor substrate shared by the entire integrated circuit. The severity of this noise coupling problem therefore depends upon how efficiently noise generated by a particular transistor is coupled to the substrate.
Digital circuits employ metal-oxide-semiconductor (“MOS”) transistors, in which a gate conductor is arranged upon a gate dielectric formed on the substrate. The gate dielectric is positioned laterally between source and drain regions formed in the substrate, where the source and drain regions are doped either n-type or p-type to be of opposite conductivity type to the substrate. N-type source/drain regions are used to form n-channel transistors, and p-type source/drain regions to form p-channel transistors. In complementary MOS (“CMOS”) circuits employing both n-channel and p-channel transistors, n-channel transistors are formed in p-type “wells” within the substrate, while p-channel transistors are formed in n-type wells. Such wells may be formed by selectively doping an epitaxial semiconductor layer grown upon the substrate. Doped regions can be formed in the substrate prior to growth of the epitaxial layer, thereby creating a “buried layer” beneath a well formed in the epitaxial layer. Such buried layers are typically heavily-doped layers having the same conductivity type as the overlying well. For example, an n+ (heavily-doped n-type) buried layer may underlie an n-type well, while a p+ buried layer underlies a p-type well. A buried layer may advantageously reduce the resistance of a well, facilitating electrical connection of the well to a particular voltage using a topside contact. This may be particularly important for wells containing bipolar transistors, as in a BiCMOS process combining bipolar and MOS transistors, since the well may serve as the collector region of the bipolar transistor. If buried layers of one conductivity type are used in a circuit, then buried layers of the other type are typically also included to provide electrical isolation between adjacent wells of the same conductivity type.
Integrated circuits are often formed on p-type silicon substrates. For circuits formed on a p-type substrate using buried layers such as those described above, direct resistive coupling through a p+ buried layer exists between the p-type wells used for n-channel transistors and the p-type substrate. It would therefore be desirable to develop a method and structure for reducing noise coupling of such transistors.
SUMMARY OF THE INVENTION
The problems outlined above are in large part addressed by an integrated circuit structure and method in which a buried layer having conductivity type opposite to that of the overlying well is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. For example, an n+ buried layer may be used beneath p-type wells containing noise-prone transistors formed over a p-type substrate. Such noise-prone transistors may include n-channel output buffer transistors, which may be larger and switch more current than other n-channel transistors in the integrated circuit, or semiconductor die. A doped annular region of the same conductivity type as the buried layer may be formed to laterally surround the transistor and make contact to the buried layer. In an embodiment, the buried layer of opposite conductivity type than the well is used only below wells which are of the same conductivity type as the substrate and contain output transistors. An integrated circuit containing such output transistors may also include analog circuit portions.
In an embodiment of the integrated circuit contemplated herein, metallization may be included to connect the doped annular region to one polarity (either most positive or most negative) of a supply voltage of the integrated circuit. Similarly, metallization may be included in the integrated circuit to connect the well region to one polarity of the supply voltage. These voltage polarities may be such that a p-n junction between the doped annular region and the well is reverse-biased. In such an embodiment, therefore, the metallization may be adapted to connect opposite-polarity supply voltages to the well and doped annular regions. Reverse-biasing the junction between the buried layer and the well may in some cases disadvantageously cause depletion regions within the well to merge below the transistor, however, possibly allowing carrier movement between the transistor and the buried layer and/or annular region. In other embodiments, therefore, the metallization may be adapted to leave the doped annular region floating or to connect it to the same voltage polarity as the well. In still a further embodiment, the buried layer may be formed in two portions: a central portion underlying the transistor, and a separate portion spaced apart from and laterally surrounding the central portion. A doped annular region surrounding the transistor may contact the outer portion of the buried layer. In such an embodiment, the central portion of the buried layer remains electrically “floating” regardless of the voltage applied by a topside contact to the doped annular region.
In an embodiment of a method contemplated herein for forming an integrated circuit, a well region is formed over a doped structure formed within a semiconductor substrate, where the well region is of the same conductivity type as the substrate and the doped structure is of opposite conductivity type than the substrate. A transistor may be formed in the well region. A doped annular region of the same conductivity type as the doped structure may further be formed surrounding the well region to contact the underlying doped structure. In an embodiment, metallization may be formed, where the metallization is adapted to connect the doped annular region and the well region to opposite polarities of a supply voltage. In an alternative embodiment, metallization adapted to preclude connection of the doped annular region and the well region to opposite polarities of a supply voltage may be formed. In a further embodiment, the doped structure may include a first portion and a second portion spaced apart from and laterally surrounding the first portion. In such an embodiment, a doped annular region may be formed to make contact to the second portion of the doped structure.
The integrated circuit and method described herein may advantageously reduce noise coupling of output transistors into the semiconductor substrate by providing substrate isolation for wells of the same conductivity type as the substrate and containing such output transistors. The performance of analog circuit portions included in the same semiconductor die may therefore be improved. The buried layer embodiments described herein may be formed by modifying the buried-layer mask typically used in BiCMOS/CMOS integrated circuit formation. Therefore, no additional masks are required to implement the integrated circuit and method.


REFERENCES:
patent: 4799098 (1989-01-01), Ikeda et al.
patent: 4814288 (1989-03-01), Kimura et al.
patent: 4862242 (1989-08-01), Wildi et al

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