Buried gate JFET

Fishing – trapping – and vermin destroying

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437 38, 437 78, 437 79, 437228, H01L 2144, H01L 2148

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active

048450510

ABSTRACT:
A process for manufacturing a JFET in accordance with our invention includes the steps of forming an N- layer (12) on an N+ substrate (10), and forming an N+ layer (14) on the N- layer. A plurality of trenches (19) are etched to extend through the N+ layer and through a portion of the N- layer. A layer of sidewall oxide (20) is grown along the vertical walls of the trenches. The trenches are then extended so that the sidewall oxide only covers a portion of the vertical walls of the trenches. A layer of P type polysilicon (22) is then deposited in the trenches and impurities are diffused from the P type polysilicon into a surrounding portion of the N- layer to thereby form a plurality of P type regions (23). The size of the depletion region between the P type regions and the N- layer is controlled by applying selected voltages to the P type polysilicon, thereby controlling the current through the resulting JFET.

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Ting, "Silicide for Contacts and Interconnects", International Electronics Device Meeting 1984, pp. 110-113.
Kim et al., "Mo/TiW Contact for VLSI Applications", International Electronic Device Meeting 1984, pp. 134-137.
Sachdev et al., "CVD Tungsten and Tungsten Silicide for VLSI Applications", Semiconductor International, May, 1985, pp. 306-310.

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