Buried digit line stack and process for making same

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S754000, C257S763000

Reexamination Certificate

active

06614116

ABSTRACT:

FIELD OF THE INVENTION
The field of the invention relates to semiconductor processing. More particularly, one embodiment relates to a process of making an electrical coupling between semiconductive material and a metal. In particular, an embodiment relates to a process for making a tungsten buried digit line (“WBDL”) stack.
BACKGROUND
Semiconductor processing is an intensive activity during which several processes are integrated to achieve a working device. Miniaturization is the process of crowding more semiconductive devices onto a smaller substrate area in order to achieve better device speed, lower energy usage, and better device portability, among others. New processing methods must often be developed to enable miniaturization to be realized. The advent of the buried digit line (“BDL”) allowed for a lower overall profile of a dynamic random access memory (“DRAM”) device. However, the average grain size (“gs”) of a metallization continues to decrease in a manner that causes grains to form that follow the grain boundaries of a substrate. Accordingly, a higher than desirable resistivity persists despite miniaturization.
One challenge is to prevent metal agglomeration during back-end-of-line (“BEOL”) processing. The challenge to achieve digit line communication in a memory device that has a low resistivity, is often accompanied by the challenge to achieve a temperature-resistant digit line that is protected from the encroachment of damaging elements during BEOL processing, burn-in testing, and field use. Thus, what is needed is a conductive structure that overcomes some of the challenges of the prior art.
SUMMARY
The above mentioned problems and challenges are overcome by embodiments of this invention. One embodiment is directed to a process of forming a tungsten buried digit line (“WBDL”) stack on a substrate. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug. Next, a metal silicide nitride second film is formed by reactively sputtering a silicon-rich metal silicide target with a nitrogen gas. The metal silicide nitride second film is covered with a tungsten third film. A salicidation process causes the first film to salicide with the polysilicon plug. In one embodiment, all the aforementioned deposition processes are carried out by physical vapor deposition (“PVD”).
In another embodiment, a process of forming a WBDL stack is carried out on a substrate. The process includes forming a silicon-lean metal silicide first film over a polysilicon plug. Next, a titanium nitride second film is formed by sputtering a titanium nitride target above the first film. The titanium nitride second film is covered with a tungsten third film. A salicidation process causes the first film to salicide with the polysilicon plug.
Because the buried digit line structures of active devices are formed according to embodiments of the present invention, a lower resistivity and a higher thermal processing yield are achieved.
Another embodiment relates to a device that includes a BDL structure. The device is packaged and implemented in a host. In one embodiment, the host includes a memory module, In another embodiment, the host includes a computer system with a processor, a memory system, and at least one I/O device connected to the host.


REFERENCES:
patent: 5392189 (1995-02-01), Fazan et al.
patent: 5717250 (1998-02-01), Schuele et al.
patent: 5892254 (1999-04-01), Park et al.
patent: 6162671 (2000-12-01), Lee et al.
patent: 6455424 (2002-09-01), McTeer et al.
patent: 6531730 (2003-03-01), Sandhu et al.

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