Buried contacts for N and P channel devices in an SOI-CMOS proce

Details Buried contacts for N and P channel devices in an SOI-CMOS proce Buried contacts for N and P channel devices in an SOI-CMOS proce

1984-05-24

1986-11-04

James, Andrew J.

357 86, 357 71, H01L 2702

Patent

active

046212760

ABSTRACT:
The disclosure relates to a method for realizing a fully functional buried level of interconnect using only a single level of a silicide over N+ polycrystalline silicon, the latter serving as the gate material for both the N channel and P channel devices formed.

REFERENCES:
patent: 4276688 (1981-07-01), Hsu
patent: 4333099 (1982-06-01), Tanguay
patent: 4374700 (1983-02-01), Scott
patent: 4509991 (1985-04-01), Taur

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