Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Bulk effect switching in amorphous material
Reexamination Certificate
1998-05-11
2001-05-01
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Bulk effect device
Bulk effect switching in amorphous material
C257S327000, C257S328000, C257S329000, C257S335000
Reexamination Certificate
active
06225642
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87,105,996, filed Apr. 20, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a vertical double-diffusion MOS (VDMOS). More particularly, the present invention relates to a VDMOS that incorporates a buried channel.
2. Description of Related Art
FIG. 1
is a cross-sectional view showing a conventional vertical double-diffuision MOS (VDMOS) structure. As shown in
FIG. 1
, the VDMOS structure is formed by forming an epitaxial layer over a substrate
100
. The epitaxial layer is doped with N+ and acts as the drain region
102
of the VDMOS. Next, an N+ doped polysilicon gate
104
is formed over the substrate
100
. A channel region
106
is formed above the drain region
102
. The channel region
106
and the gate
104
are separated by a gate oxide layer
108
. The source region
110
is located between neighboring gates above the channel region
106
. The channel region
106
further includes an N doped main region
106
a,
a first P-doped region
106
b,
and a second P-doped region
106
c.
The first P-doped region
106
b
is located between neighboring gates
104
above the main region
106
a,
and a portion of the first region
106
b
extends into a region underneath the gate
104
. The second P-doped region
106
c
borders on the first region
106
b
below the source region
110
so that the second region
106
c
is separated from the source region
110
by the first region
106
b.
In
FIG. 1
, a channel is formed in the VDMOS transistor when a high voltage is applied to the gate terminal
104
. Therefore, electrons can flow from the source region
110
via the first region
106
b
and the main region
106
a
of the channel region
106
towards the drain region
102
, thereby forming a conductive circuit. Since the N-type channel of the VDMOS transistor is formed on the surface of the first region
106
b,
a number of drawbacks related to an NMOS transistor will occur. Examples include the lowering of electron mobility in the channel due to the high electric field created by the gate
104
, and the hot carrier effect due to the flow of a high current. These drawbacks result from the channel in the source region
110
formed by free electrons being too close to the substrate
100
. When electron mobility is low, not only does the operating time of the device increase, but a larger current is also difficult to produce.
In light of the foregoing, there is a need to improve the vertical double diffusion MOS structure.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a vertical double-diffusion MOS (VDMOS) transistor that also incorporates a buried channel structure. Besides being capable of increasing electron mobility inside the channel, the buried channel is able to lower the capacitor effect between the gate and the substrate of the transistor and reduce the hot carrier effect, and hence increases the speed and the reliability of the device.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a buried channel vertical double-diffusion MOS device. The MOS device comprises a substrate, a drain region, a gate region, a source region and a channel region. The drain region is located above the substrate and the gate region is above the substrate surface. The source region is located between two neighboring gates in the substrate. The channel region is located above the drain region separated from the gate by a gate-insulating layer. The channel region further includes a main region, a buried channel region, a first region and a second region. The buried channel region is located below the gate-insulating layer. The buried channel region is impurity-doped so that the threshold voltage of the buried channel VDMOS device can be adjusted. The first region is located between two neighboring gates in the substrate lying next to the drain region with portion of it extending into a region underneath the gate. The second region is located below the source region next to the first region, but the second region does not have direct contact with the source region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 3673471 (1972-06-01), Klein et al.
patent: 5055895 (1991-10-01), Akiyama et al.
patent: 5786619 (1998-06-01), Kinzer
patent: 5877527 (1999-03-01), Okabe et al.
Abraham Fetsum
Christie Parker & Hale LLP
United Silicon Inc.
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