Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Heterojunction
Reexamination Certificate
2001-05-16
2003-04-29
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Heterojunction
C257S019000, C257S192000, C257S274000
Reexamination Certificate
active
06555839
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to the field of buried channel strained-Si FETs, and in particular to these FETs using a supply layer created through ion implantation.
The advent of relaxed SiGe alloys on Si substrates introduces a platform for the construction of new Si-based devices. These devices have the potential for wide application due to the low cost of using a Si-based technology, as well as the increased carrier mobility in strained layers deposited on the relaxed SiGe.
As with most new technologies, implementing these advances in a Si CMOS fabrication facility requires additional innovation. For example, some of the potential new devices are more easily integrated into current Si processes than other devices. Since process technology is directly relevant to architecture, particular innovations in process technology can allow the economic fabrication of new applications/architectures.
FIGS. 1A and 1B
are schematic block diagrams showing the variety of strained Si devices that are possible to fabricate given the advent of relaxed SiGe buffer layers.
FIG. 1A
shows a surface channel strained Si MOSFET
100
. In this configuration, a tensile, strained Si channel
102
is deposited on relaxed SiGe layer
104
with a Ge concentration in the range of 10-50%. This relaxed SiGe layer is formed on a Si substrate
108
through the use of a compositionally graded SiGe buffer layer
106
. A conventional MOS gate stack
110
is on the strained silicon channel and consists of an oxide layer
112
, a poly-Si electrode
114
, and a metal contact layer
116
. Doped source
118
and drain
120
regions are also formed on either side of the gate stack to produce the MOSFET device structure.
A buried channel strained Si high electron mobility transistor (HEMT)
130
is shown in FIG.
1
B. In this configuration, the strained Si
102
atop the relaxed SiGe
104
has been capped with a thin SiGe cap layer
132
. The strained Si layer generally has a thickness between 2-30 nm, while the SiGe cap layer has a thickness between 2-20 nm. A metal Schottky gate
134
on the SiGe cap layer is commonly used on the HEMT, and, as in the MOSFET structure, doped source
118
and drain
120
regions are formed on each side of this gate.
FIG. 1C
shows a buried channel strained Si MOSFET
140
. This device has the same Si/SiGe layer structure as the HEMT configuration, but with a full MOS gate stack
142
, consisting of oxide
144
, poly-Si
146
, and metal
148
layers, rather than the metal Schottky gate.
It is important to separate these devices into two categories, surface channel devices, of which an embodiment is shown in
FIG. 1A
, and buried channel devices, of which embodiments are shown in
FIGS. 1B and 1C
. In the case of the surface channel device, a light background doping in the SiGe during epitaxial growth or by implantation is sufficient to position the Fermi level such that a MOSFET constructed from the strained surface channel has reasonably large threshold values. Thus, the surface can be inverted for either p or n channel operation.
FIGS. 2A and 2B
are the energy band diagram for the case of the surface channel FET for an NMOS device, (A) at zero bias, and (B) at a bias to turn on the transistor, respectively. When the transistor is turned on, a relatively large electric field exists in the normal direction to the surface plane, and the electrons are attracted to the surface and operate in the strained Si surface channel. The speed of the transistor is increased due to the fact that the electrons reside in the high mobility, strained Si surface channel. However, the device has noise performance similar to a conventional Si MOSFET since the carriers scatter off the SiO
2
/Si interface, and the device, although it possesses a mobility larger than that of a conventional Si device, still has a mobility that is limited by the SiO
2
/Si interface.
However, it is known from III-V materials that a buried channel device should possess a much higher electron mobility and lower noise performance. For example, the structures shown in
FIG. 1B and C
should have higher channel mobility and lower noise performance than the device in
FIG. 1A
since the electron scatters off a semiconductor interface instead of an oxide interface.
A crucial flaw in the device shown in
FIG. 1C
that leads to processing difficulties and limitations in circuit layout and architectures is that when the device is biased to invert the channel and turn the device on, the band structure is such that many of the carriers leave the buried channel.
FIG. 3
is an energy band diagram showing schematically the problem with a buried channel device in which there is no dopant supply layer. The field required to turn on the device empties the buried channel. This effectively creates a surface channel device even though the buried channel layer is present in the heterostructure.
The applied gate bias of
FIG. 3
has bent the bands such that many of the electrons from the well escape confinement and create an inversion layer at the oxide/semiconductor interface. Since transconductance of a field effect device is high if the mobility and the number of carriers is high, a high performance FET, i.e., even higher performance than the surface channel device, is difficult to achieve. At low vertical fields, the electrons are in the high mobility buried channel, but there are few in number. If the device is turned on and inverted as shown in
FIG. 3
, the carrier density in the surface channel is high but the mobility is reduced since the carriers are now at the rough oxide interface.
One way to solve this problem is to insert a dopant supply layer into the structure, as shown in FIG.
4
A.
FIG. 4A
is a schematic block diagram of a structure
400
in which the buried channel can be occupied with a high density of electrons via the insertion of a layer of donor atoms. It will be appreciated that an equivalent schematic can be constructed for a buried hole channel with a layer of acceptor atoms.
The structure
400
includes a strained Si channel
402
positioned between two SiGe layers, a relaxed SiGe layer
404
and a thin SiGe cap layer
406
. Although
FIG. 4A
shows a dopant supply layer
408
in the SiGe cap, the dopants can be introduced into either SiGe layer. As has been shown in the III-V buried channel devices, this layer configuration creates a band structure where now the buried channel is occupied, as shown in FIG.
4
B. In this figure, the supply layer leads to localized band bending and carrier population of the buried strained Si. In the strained Si, the conduction band has been lowered beneath the Fermi level, resulting in a high carrier density in the high mobility channel. One disadvantage of this structure is that now the transistor is on without any applied voltage, and a voltage is supplied to the gate to turn off the transistor. Thus, this transistor is normally on or depletion-mode. As a result, the device is useful in analog and logic applications, but is not easily implemented in a conventional CMOS architecture.
Common accepted practice in the buried channel heterostructure FETs is to use a dopant supply layer that is introduced in an epitaxial step, i.e., deposited during the epitaxial process that creates the Si/SiGe device structure. This dominant process originates from the III-V research device community (AlGaAs/GaAs materials system). However, this epitaxial dopant supply layer is undesirable since it reduces thermal budget and limits the variety of devices available in the circuit. For example, if the dopant supply layer is introduced in the epitaxial step, when processing begins, the thermal budget is already constrained due to diffusion of the supply layer dopants. All devices in the circuit must also now be buried channel devices with similar thresholds, since any removal of the dopant layer in a particular region would require complete etching of the local area and removal of critical device regions.
SUMMARY OF THE INVENTION
In accordance with the invention, there is provided a de
AmberWave Systems Corporation
Ho Tu-Tu
Nelms David
Testa Hurwitz & Thibeault LLP
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