Buried bit-line source-side injection flash memory cell

Fishing – trapping – and vermin destroying

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437 49, 437 50, H01L 2906, H01L 2968, H01L 2976, H01L 2926

Patent

active

052847845

ABSTRACT:
The present invention provides a flash EPROM cell structure that has the advantages of source-side injection, but which is formed in such a way as to allow it to be utilized in a virtual-ground buried bit-line array layout. The buried bit-line array confers two advantages over the more conventional T-cell array. It allows contacts to be shared among a large number of cells, thereby reducing the layout area associated with each cell. This leads to smaller chip size. Moreover, the yield of the array is significantly increased due to the drastic reduction in the total number of contacts in the array.

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K. Naruke, et al.; A New Flash-Erase EEPROM Cell with a Sidewall Select-Gate on its Source Side; IEEE 1989; IEDM 89 pp. 603-606.
A. T. Wu; A Novel High-Speed, 5-volt programming EEPROM Structure with Source-Side Injection; IEEE 1986; IEDM 86 pp. 584-587.

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