Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Reexamination Certificate
2001-05-10
2002-11-05
Talbott, David L. (Department: 2827)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
C438S123000, C438S612000
Reexamination Certificate
active
06475833
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a semiconductor device assembly, and in particular, to a chip assembly which includes a single or multi-layered substrate of which circuitry traces are connected to the input/output terminal pads of the IC chip through deposition of conductive material into substrate via holes and onto preformed leads and the terminal pads.
BACKGROUND OF THE INVENTION
Recent developments of semiconductor packaging suggest an increasingly critical role of the technology. New demands are coming from requirements for more leads per chip and hence smaller input/output terminal pad pitch, shrinking die and package footprints, and higher operational frequencies that generate more heat, thus requiring advanced heat dissipation designs. All of these considerations must be met and, as usual, are placed in addition to the cost that packaging adds to the semiconductor manufacturing food chain.
Conventionally, there are three predominant chip-level connection technologies in use for integrated circuits, namely, wire bonding, tape automated bonding (TAB) and flip chip (FC), to electrically or mechanically connect integrated circuits to leadframe or substrate circuitry. Conventional flip chip technology is characterized as mounting of an unpackaged semiconductor chip with the active side facing down to an interconnect substrate through contact anchors such as solder, gold or organic conductive adhesive bumps. The major advantage of flip chip technology is the short interconnects, which, therefore, can handle high speed or high frequency signals. There are essentially no parasitic elements, such as inductance. Not only is the signal propagation delay slashed, but much of the waveform distortion is also eliminated. Flip chip also allows an array interconnecting layout that provides more I/O than a perimeter interconnect with the same die size. Furthermore, it requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space is used. An example of such a method is disclosed in U.S. Pat. No. 5,261,593 issued to Casson et al.
While flip chip technology shows tremendous advantages over wire bonding, its cost and technical limitations are significant. First of all, prior art flip chip technology must confront the challenge of forming protruded contact anchors or bumps to serve as electrical connections between the integrated circuit chip and substrate circuitry. Examples of such an approach are disclosed in U.S. Pat No. 5,803,340 issued to Yeh et al. and U.S. Pat. No. 5,736,456 issued to Akram. They typically include a very costly vacuum process to deposit an intermediate under-bump layer that serves as an adhesive and diffusion barrier. This barrier layer is typically composed of a film stack that can be in the structure of chromium/copper/gold. Bumping materials such as solder are subsequently deposited onto this intermediate layer through evaporation, sputtering, electroplating, solder jetting or paste printing methods followed by a reflow step to form the solder contacts.
Although evaporation and sputtering can potentially offer high density bumps, these processes need very tight control and normally result in a poor yield. In addition, from the mechanical structure viewpoint, the coefficient of thermal expansion (CTE) of silicon and the substrate may be quite different, causing the stress between these two parts after attachment to build up and become fully loaded on the bumps. This can then cause severe joint cracking and disconnection problems during normal operating conditions. As a result, a conventional flip chip assembly is not only very costly but also suffers from very serious reliability problems and a high fatality ratio.
Organic contacts, which utilize conductive adhesive to replace solder, are described in U.S. Pat. No. 5,627,405 issued to Chillara and U.S. Pat. No. 5,611,140 issued to Kulesza et al. Generally speaking, the conductive adhesive which is made by adding conductive fillers to polymer binders holds a number of technical advantages such as environmental compatibility, lower temperature processing capability, fine pitch and simplified processes compared to soldering. However, conductive adhesives do not normally form a metallurgical interface in the classical sense. The basic electrical pathway is through conductive particles of the adhesives that are in contact with one another and reach out to the two contact surfaces of the components.
In view of the limitations of currently available integrated circuit assembling methods, a high performance, reliable and economical method that can effectively interconnect integrated circuits to the external circuitry would be greatly desirable.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a flip chip assembly to address high density, low cost and high performance requirements of semiconductor packaging. The present invention involves the bonding of substrate circuitry to a semiconductor device through the connection of preformed leads inside the via apertures or holes to IC terminal pads beneath the via holes without the need for conventional bumps, bonding wire, or other media. This provides both electrical and mechanical connection between the IC chip and circuitry of the substrate.
In accordance with an aspect of the invention, a flip chip assembly includes a semiconductor chip including a terminal pad, a substrate including a dielectric layer and an electrically conductive trace, wherein the dielectric layer includes first and second surfaces that are opposite one another and a via hole that extends between the first and second surfaces, the conductive trace is disposed on the first surface and bent proximate to a corner between the first surface and the via hole at a different angle than the corner and extends into the via hole without extending to the second surface and without contacting the terminal pad, the via hole is aligned with the terminal pad, and the second surface is attached to the chip, and an electrically conductive material in the via hole that contacts the conductive trace and electrically connects the conductive trace to the terminal pad.
Preferably, the conductive trace laterally extends across a majority of a diameter of the via hole and vertically extends across a majority of a depth of the via hole and contacts substantially none of the dielectric layer at sidewalls of the via hole, the conductive material contacts substantially all of the dielectric layer at sidewalls of the via hole, substantially all of the conductive material is within the via hole, and the conductive trace and the conductive material are the only materials in the via hole. Suitable conductive materials include conductive adhesives and solder.
Using extended leads and conductive material directly deposited in the via hole can effectively connect the IC chip and substrate circuitry without external bumps or wires. This approach allows a highly reliable, low profile, high performance and low cost assembly to be achieved. In particular, a small via hole formed by laser drilling or other techniques allows a very fine pitch terminal pad to be interconnected, which can significantly enhance the capability of packaging future high I/O semiconductor chips.
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pa
Chambliss Alonzo
Sigmond David M.
Talbott David L.
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