Bumping process and bump structure

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C438S614000

Reexamination Certificate

active

07545038

ABSTRACT:
A bumping process comprises forming a passivation layer having a planarized surface covering a pad on a substrate, forming a hole penetrating through the passivation layer to expose a contact surface of the pad, and forming a bump on the contact surface and planarized surface. The planarized surface will provide a larger effective area for pressing, thereby minimizing the pad, enhancing the mechanical strength at the peripheral of the pad, providing more selection flexibility for anisotropic conductive film, reducing the possibilities of short circuit and current leakage within the bump gap, and increasing the yield of the pressing process and the conductive quality of the bump.

REFERENCES:
patent: 6372619 (2002-04-01), Huang et al.
patent: 6479376 (2002-11-01), Huang et al.
patent: 7282433 (2007-10-01), Tang et al.

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