Bump with multiple vias for semiconductor package and...

Details Bump with multiple vias for semiconductor package and... Bump with multiple vias for semiconductor package and...

2011-07-12

2011-07-12

Richards, N Drew (Department: 2895)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257SE21509, C257SE23023

Reexamination Certificate

active

07977789

ABSTRACT:
A bump for a semiconductor package forms a polymer layer having multiple vias on an electrode pad above a semiconductor chip to increase an electrical contact area between the electrode pad and a metal bump. Further, the bump forms a polymer layer having multiple vias on a redistribution electrode pad to increase a surface area of an electrode interconnection. The multiple vias increase electrical and mechanical contact areas, thereby preventing current crowding and improving joint reliability. The bump for a semiconductor package may further comprise a stress relaxation layer at the lower portion of the bump.

REFERENCES:
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patent: 2006/0125110 (2006-06-01), Do et al.
patent: 2007/0001301 (2007-01-01), Wang
patent: 2007/0020906 (2007-01-01), Chiu et al.
patent: 2007/0075423 (2007-04-01), Ke et al.
patent: 2000311913 (2000-11-01), None
patent: 2004363319 (2004-12-01), None
patent: 20000065487 (2000-11-01), None

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