Metal fusion bonding – Process – Plural joints
Reexamination Certificate
2002-05-03
2004-12-07
Edmondson, L. (Department: 1725)
Metal fusion bonding
Process
Plural joints
C228S180100, C228S180210, C257S737000
Reexamination Certificate
active
06827252
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority benefit of Taiwan application serial no. 91102992, filed Feb. 21, 2002.
BACKGROUND OF INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing bumps. More particularly, the present invention relates to a bump manufacturing method capable of strengthening the bond between a solder block and a silicon wafer.
2. Description of Related Art
In this information explosion age, electronic products are used almost everywhere. Computer and processing stations driven by powerful integrated circuits are employed in offices, educational institutions, recreational industries, business and commercial companies. As electronic technology continues to progress, products having more powerful functions and more attuned to personal needs are developed. Furthermore, most electronic products are increasingly light and compact thanks to the efficient fabrication of many types of high-density semiconductor packages. A major innovation is the flip chip design capable of cramming a considerable number of integrated circuits together. In a flip-chip design, a plurality of bumps is formed on the bonding pads of a silicon chip. Each bump directly contacts a corresponding contact point on a substrate so that the chip and the substrate are electrically connected. Compared with conventional wire bonding and tape automated bonding (TAB) methods of joining a chip with a substrate, the flip-chip design has a shorter overall conductive path and hence a better electrical connectivity. In addition, the backside of the chip may be exposed to facilitate heat dissipation during operation. Due to the distinguishing advantages of flip-chip packages, semiconductor manufacturing favors its production.
FIGS. 1
to
4
are partially magnified cross-sectional views showing the steps for forming bumps on a silicon wafer according to a convention method. As shown in
FIG. 1
, a silicon wafer
110
having an active surface
112
is provided. The wafer
110
also has a passivation layer
114
and a plurality of bonding pads
116
(only one is shown) over the active surface
112
of the wafer
110
. The passivation layer
114
exposes the bonding pads
116
. A conventional stud-forming machine is used to form a first solder block
120
over each solder pad
116
. The first solder blocks
120
are made from a material such as copper or gold. The upper surfaces
122
of the first solder blocks
120
are planarized to form a structure as shown in FIG.
2
.
As shown in
FIG. 3
, a conventional wire-bonding machine is used to attach a second solder block
130
to the upper surface of the first solder block
120
. The second solder blocks
130
are made from a material such as lead-tin alloy. A reflow operation is carried out sprinkling a flux material over the wafer and heating the wafer. The heat softens the second solder blocks
130
and transforms the second solder blocks
130
into blobs of material having a hemispherical profile as shown in FIG.
4
. This completes the fabrication of a bump
140
(only one is shown) comprising one first solder block
120
and one second solder block
130
.
In the aforementioned fabrication process, the first solder block
120
directly bonds with the bonding pad
116
. Hence, the first solder block
120
and the bonding pad
116
must have good bondability. However, not every type of material constituting the first solder block
120
has the capacity to wet the bonding pad
116
material. Thus, there is limitation in the selection of material forming the first solder blocks
120
. Improper selection of first solder block material may result in the formation of a weak bond with the bonding pads
116
. Furthermore, some of the first solder block material such as copper has great diffusion capacity. Such metallic particles may diffuse into the wafer forming unwanted conductive circuits between metallic interconnects inside the wafer. In some cases, the chip may fail because of this, leading to a lower production yield.
SUMMARY OF INVENTION
Accordingly, one object of the present invention is to provide a method of forming bumps over a silicon wafer such that an additional under-ball metallic layer is formed between a bonding pad on the wafer and a first solder block. Hence, ultimate adhesive strength of the bump with corresponding bonding pad is increased.
A second object of this invention is to provide a method of forming bumps over a silicon wafer such that an additional under-ball metallic layer is formed between a bonding pad on the wafer and a first solder block. Hence, the diffusion of metallic particles inside the bump into the wafer is prevented and the probability of chip failure due to short circuit is reduced.
Note in the following description that the use of the preposition “over” as in “a second layer is formed over a first layer” means that the second layer is either in contact with the first layer or simply above the first layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming a plurality of bumps over a silicon wafer. The wafer has an active surface with a passivation layer and a plurality of bonding pads thereon. The passivation layer exposes the bonding pads. First, an adhesion layer is formed over the active surface of the wafer covering the bonding pads and the passivation layer. A barrier layer is formed over the adhesion layer. A wettable layer is formed over the barrier layer.
A photolithographic process is conducted to from a plurality of photoresist blocks over the wettable layer. A first etching operation is carried out to remove the wettable layer, the barrier layer and the adhesion layer outside the photoresist blocks so that only the wettable layer, the barrier layer and the adhesion layer underneath the photoresist blocks remain. The photoresist blocks are removed.
A first solder block bonds onto the wettable layer through a bonding operation. Each first solder block has an upper surface and a lower surface. The lower surface of the first solder block bonds with the wettable layer. The upper surface of the first solder block is planarized through polishing. Thereafter, a second solder block bonds onto the upper surface of the first solder block through another bonding operation. A reflow operation is next carried out.
According to the embodiment of this invention, the adhesion layer can be made from a material including titanium, titanium-tungsten alloy, aluminum or chromium. The barrier layer can be made from a material including nickel-vanadium alloy, chromium-copper alloy or nickel. The first solder block can be made from a material including lead-tin alloy, tin-silver alloy, tin-silver-copper alloy, silver or gold. The second solder block can be made from a material including lead-tin alloy, tin-silver alloy, tin-silver-copper alloy or tin.
In addition, after bonding a second solder block onto a first solder block, the upper surface of the second solder block may be planarized through polishing. The reflow operation is carried out after the planarization. However, the process of planarizing the upper surface of the second solder block can also be omitted entirely.
In brief, because the first solder block is bonded onto the wettable layer, a material capable of wetting the first solder block may be chosen as the material constituting the wettable layer. Hence, the first solder blocks are tightly coupled to the wafer. The under-ball metallic layer may be designed according to the material constituting the first solder blocks so that solder blocks of whatever material can attach firmly to the active surface of the wafer. Furthermore, through the placement of an under-ball metallic layer, diffusion of metallic particles from the solder block to the wafer is blocked. Hence, the diffusion of metallic particles into the insulation layer of the wafer leading to chip failure is greatly minimized. Moreover, different types of materials may b
Chen Jau-Shoung
Fang Jen-Kuang
Huang Min-Lung
Lee Chun-Chi
Lee Yung-Chi
Advanced Semiconductor Engineering Inc.
Edmondson L.
Jiang Chyun IP Office
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