Built-in test feature to facilitate system level stress...

Details Built-in test feature to facilitate system level stress... Built-in test feature to facilitate system level stress...

2005-01-13

2009-11-03

Liu, Shuwang (Department: 2611)

Pulse or digital communications

Testing

Phase error or phase jitter

C375S354000, C375S219000, C375S373000, C324S763010

Reexamination Certificate

active

07613237

ABSTRACT:
A method of ensuring robust operation of a differential serial link is provided. The method provides a first integrated circuit having 1) a phase generator constructed and arranged to provide a programmable shift of a clock signal based on selective interpolating between first and second phases of the clock signal relative to a digital phase value, and 2) a transmit driver constructed and arranged to control, in a programmable manner, a differential voltage of digital data signals. A second integrated circuit is constructed and arranged to receive the clock and digital data signals sent by the first integrated circuit. The clock and digital data signals are sent substantially simultaneously through the link from the first integrated circuit to the second integrated circuit. It is determined whether the digital data signals can be sampled reliably by the second integrated circuit relative to the digital phase value. The clock signal is shifted, based on changing the digital phase value supplied to phase generator, towards a transition of the data signals until a failure is detected relative to an identified phase value such that the digital data signals cannot be sampled reliably by the second integrated circuit. Based on detection of the failure relative to the corresponding identified phase value, a time margin of the clock signal is established wherein the digital data signals can be sampled reliably by the second integrated circuit. A voltage margin of the differential voltage is also provided.

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