Built-in test circuitry providing simple and accurate AC test of

Horology: time measuring systems or devices – Time interval – Electrical or electromechanical

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Details

368118, 368120, 324 731, G04F 800, G01R 1512

Patent

active

051811910

ABSTRACT:
Circuitry and techniques are for transferring data between the automatic test equipment (ATE) and an integrated circuit under test pursuant to a slow clock that can have an arbitrarily long period, and for operating storage elements in the integrated circuit pursuant to a fast clock having a short period that corresponds to the clock rate at which combinatorial networks in the integrated circuit are to be tested. In one embodiment, input latches at inputs of the integrated circuit receive test data from the ATE, and output latches at the outputs provide test result data for the ATE. Pursuant the alternating single cycles of the slow clock and the fast clock, the delays through combinatorial networks between of a data propagation path between an input latch and an output latch are tested pursuant to the fast clock. In another embodiment, test data is serially scanned into scan registers pursuant to a series of slow clock cycles. After the test data has been scanned in, the scan registers are operated parallel to test the delays of combinatorial networks between the scan registers.

REFERENCES:
patent: 4736351 (1988-04-01), Oliver
patent: 4841500 (1989-06-01), Lee
patent: 4878209 (1989-10-01), Bassett et al.
patent: 4890270 (1989-12-01), Griffith
patent: 5083299 (1992-01-01), Schwanke et al.

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