Built-in test circuit connection for wafer level burnin and test

Details Built-in test circuit connection for wafer level burnin and test Built-in test circuit connection for wafer level burnin and test

1992-04-10

1993-08-31

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

371 225, G01R 3128

Patent

active

052412660

ABSTRACT:
Integrated circuit devices are fabricated with an additional conductive layer deposited on a semiconductor wafer onto which the semiconductor devices have been formed. The additional layer provides a conductive path to power the test circuits and allows the use of very few electrical connections in order to permit testing of the devices while still on the wafer. The ability to test the devices while still on the wafer facilitates burning in the wafer prior to singulating the parts, since it is not necessary to establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment of the invention, the additional conductive layer is a metal mask and in a further aspect of that embodiment permits external connections to be accomplished at locations outside the die areas, thereby avoiding damage to the integrated circuit devices. Subsequent to testing of the die in wafer form, the metal mask is stripped and the die may be singulated.

REFERENCES:
patent: 3781683 (1973-12-01), Freed
patent: 3803483 (1974-04-01), McMahon, Jr.
patent: 3849872 (1974-11-01), Hubacher
patent: 4956602 (1990-09-01), Parrish
patent: 4961053 (1990-10-01), Krug
patent: 5059899 (1991-10-01), Farnworth et al.
patent: 5142224 (1992-08-01), Smith et al.

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