Built-in-test by signature inspection (bitsi)

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371 151, 371 251, 371 27, G06F 1100

Patent

active

050519964

ABSTRACT:
A system and method for fault detection for electronic circuits. A stimulus generator sends a signal to the input of the circuit under test. Signature inspection logic compares the resultant signal from test nodes on the circuit to an expected signal. If the signals do not match, the signature inspection logic sends a signal to the control logic for indication of fault detection in the circuit. A data input multiplexer between the test nodes of the circuit under test and the signature inspection logic can provide for identification of the specific node at fault by the signature inspection logic. Control logic responsive to the signature inspection logic conveys information about fault detection for use in determining the condition of the circuit. When used in conjunction with a system test controller, the built-in test by signature inspection system and method can be used to poll a plurality of circuits automatically and continuous for faults and record the results of such polling in the system test controller.

REFERENCES:
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patent: 4580274 (1986-04-01), Debany
patent: 4598401 (1986-07-01), Whelan
patent: 4817093 (1989-03-01), Jacobs
patent: 4881229 (1989-11-01), Kaltbeitzel
patent: 4897842 (1990-01-01), Herz
patent: 4910735 (1990-03-01), Yamashita

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