Built in shelf test method and apparatus for booth multipliers

Details Built in shelf test method and apparatus for booth multipliers Built in shelf test method and apparatus for booth multipliers

1996-08-09

1999-09-28

Nguyen, Hoa T.

Excavating

371 277, 371 271, G01R 3128

Patent

active

059600098

ABSTRACT:
A Built-In Self Test (BIST) method and apparatus for Booth multipliers, wherein a fixed-size (8-bit) binary counter is used along with accumulator-based output data compaction. The fault model adopted enables a BIST algorithm which is independent of specific gate level implementations of the multiplier cells. The generated 256 test vectors guarantee more than 99% single stuck-at fault coverage. A new accumulator-based compaction scheme is introduced to provide less aliasing and thus higher compaction quality than existing accumulator-based approaches. No design for testability modifications to the multiplier are required and method is totally applied on the periphery of the multiplier structure therefor causing no internal performance degradation. The BIST scheme of the present invention is generic and can be applied to any Booth multiplier derived by any module generator.

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