Built-in self tests for large multiplier, adder, or subtractor

Details Built-in self tests for large multiplier, adder, or subtractor Built-in self tests for large multiplier, adder, or subtractor

1995-10-19

1997-02-04

Beausoliel, Jr., Robert W.

Excavating

371 27, 371 251, G06F 1122, G06F 11263

Patent

active

056006586

ABSTRACT:
A method of testing a two-input multiplier, adder, or subtractor implementation for stuck-at faults includes a multi-step procedure for iteratively exercising all input and output permutations, and pseudo-exhaustively exercising all internal nodes. The method of testing a multiplier, adder, or subtractor involves logically partitioning the multiplication, addition, or subtraction into several smaller but identical independent operations. This logical partitioning of operations ensures that the output result will consist of several smaller identical results if the unit under test is functioning properly. Because the several smaller results are identical, comparing the smaller results to each other detects any failures internal to the multiplier, adder, or subtractor under test. The logically partitioned operations are repeated for multiple input setting to ensure a high level of fault coverage. In the testing of a multiplier, a four step iterative method fully exercises the multiplier. Each step includes iteratively filling alternate digits of one input operand with a first test value and filling the remaining digits of that operand with zero. Each step further includes the filling of one digit of the other multiplier operand with a second test value, while all remaining digits of that operand are filled with zero. Four different fill patterns are used for all permutations of the two test digits to fully exercise the multiplier. In the testing of an adder or subtractor, a two step iterative method fully exercises the adder or subtractor.

REFERENCES:
patent: 4866715 (1989-09-01), Van Meerbergen et al.
Sung Je Hong; The Design of testable parallel Multiplier; IEEE Trans. on computer, vol. 39, No. 3, Mar. 1990.
Fikri T. Assaad and Shantanu Dutt; More Robust tests in Algorithm-based Fault-Toleratn Matrix Multiplication; IEEE Intl. Symposium; 1992.
D. Gizopoulos, D. Nikolos, A. Paschalis, P. Kostarakis; C-Testable Multipliers based on the Modified Booth Algorithm; Asian Test Symposium 1994.
Farookh Moogat, Raymond Sifered; A 60 Mhz Asic Bit serial/parallel Multiplier; Asic conference and Exhibit; 1994.

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