Built-in self testing for the identification of faulty integrate

Details Built-in self testing for the identification of faulty integrate Built-in self testing for the identification of faulty integrate

1996-10-22

1998-04-28

Beausoliel, Jr., Robert W.

Excavating

371 225, 39518306, G01R 3128

Patent

active

057455007

ABSTRACT:
A built-in self test method and circuit identifies a faulty integrated ciit chip in a multichip module. The built-in self test method first applies a test pattern to a multichip module having a plurality of integrated circuit chips and to a reference signal generator, generates a first and second reference signal representing test responses for a fault free multichip module, compresses the outputs from the multichip module into a first and second bit using a first and second linear space compressor, uses exclusive OR logic to combine the first bit with the first reference signal to produce a first fault detection output and to combine the second bit with the second reference signal to produce a second fault detection output, stores the first and second fault detection outputs in a pair of N-bit shift registers; compares the stored outputs to detect a fault condition, and applies a series of recursive logic operations to identify the faulty integrated circuit chip in the multichip module. The built-in self test circuit includes a test pattern generator, a reference signal generator, at least two linear space compressors, at least two N-bit shift registers, and a plurality of logic gates. Identification of the faulty integrated circuit chip in an multichip module using the present invention thereby facilitates the replacement of the specific faulty chip in order to repair the multichip module.

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patent: 5442641 (1995-08-01), Beranger et al.
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patent: 5535164 (1996-07-01), Adams et al.
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patent: 5617531 (1997-04-01), Crouch et al.
patent: 5619512 (1997-04-01), Kawashima et al.

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