Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-01-12
2001-07-03
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06255836
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of built-in self-test (BIST) units for memories in integrated circuits. More particularly, this invention relates to BIST units configured to perform data retention testing in a configurable manner.
2. Description of the Related Art
Since users generally depend upon the reliability of memory chips and other integrated circuits for their own systems to function properly, it is common practice for the chip manufacturers to test the functionality of chips at the manufacturing site before the chips are sold to users. The manufacturers' reputations depend upon the reliability of their chips. As the line width within an integrated circuit chip continues to shrink, this reliability becomes more difficult to achieve. An ongoing challenge for the chip manufacturers is to increase the number and density of transistors on a chip without sacrificing reliability or suffering decreasing chip yields due to malfunctioning parts.
Before the chips are released for shipment, they typically undergo testing to verify that the circuitry for each of the major on-chip modules is functioning properly. One standard way for testing chips involves using an external memory tester or Automatic Test Equipment (ATE) at the manufacturing site. An external memory tester supplies power and applies test patterns to the chip to detect faults. External testers can only test a limited number of chips at a time, and the test speed is limited by the external bus speed. Consequently, this method of testing is expensive in terms of time requirements and equipment costs.
Partly to address these issues, and partly to provide off-site testing, built-in self-test (BIST) units are now commonly incorporated into memory chips and other integrated circuits. Automated test equipment can now be simplified to the extent that the only necessary functions are to supply power (and sometimes a clock signal) to the chip, and to monitor a single output signal from the chip. The on-board BIST unit generates all the test patterns and asserts (or de-asserts) the output signal if the chip passes the functionality test. The BIST can be configured to run every time the chip is powered-on, or the BIST may be configured to run only when a test mode signal is asserted.
A memory BIST unit operates by writing and reading various patterns to/from the memory to determine various kinds of memory faults. In general, a memory BIST unit writes a data value to a memory cell and subsequently reads the memory cell. By comparing the data written and the data subsequently returned from the memory cell, the memory BIST unit is able to determine whether the memory cell is faulty. If too many errors are detected, then the fault may exist in the support circuitry for the memory cell array.
One memory test not conducted by BIST units is an extended data retention test. In this test, an initial data pattern is written to the memory array and then verified after a measured time delay. In some variations, “disturbances” are made during the delay, such as intentionally degrading the power supply voltage. These extended data retention tests are conducted using external testers. In memories with BIST units, the external testers perform this test by controlling the clock signal to the memory chip. Enough clock cycles are provided to allow the BIST unit to write the initial data pattern, and then the clock is halted during the delay. After the delay the clock is restarted so that the BIST unit can complete its normal test sequence, thereby revealing any errors which have occurred during the delay.
Although effective, this method has two primary disadvantages. First, since it requires an external tester and detailed knowledge of the BIST algorithm, it can only be conducted by the manufacturer. Consequently, extended data retention testing is not possible in the field. Second, it can be difficult to program an external tester to place pauses at the correct points in the BIST algorithm. This is particularly true for a complex, multi-million cycle BIST routine which requires pauses in different locations. This difficulty is further compounded by the fact that when changes are made to either the BIST unit or the memory array, the pause locations must be recalculated.
SUMMARY OF THE INVENTION
Accordingly, there is disclosed herein an integrated circuit device having a BIST unit with reconfigurable data retention testing for a memory array. In one embodiment, the integrated circuit device includes a memory array, a BIST unit, an externally-programmable pause count register, and a pause counter. The BIST unit is configured to apply a test pattern of memory accesses to the memory array. The test pattern preferably includes a first phase for writing data values to the memory array, a second phase for stressing the memory array, and a third phase for verifying the data values after the array has been stressed. The length of the second phase is determined by the count stored in the eternally-programmable register. The Count may be loaded into the pause counter by the BIST prior to the second phase. In the second phase, the BIST unit asserts a pause signal which causes the pause counter to suppress the clock signal to the BIST unit during the second phase, thereby suspending the BIST unit's activity. The pause signal may also initiate “disturbances” to the memory array during the second phase, such as degrading the power supply voltage and initiating the activity of a sub-BIST unit that conducts memory accesses near a target memory location designed to “stress” that target memory location. Once the pause counter finishes counting, the clock signal to the BIST unit is reestablished, allowing the BIST unit to conduct the verification phase.
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patent: 5991213 (1999-11-01), Cline et al.
patent: 6014336 (2000-01-01), Powell et al.
Irrinki V. Swamy
Schwarz William
LSI Logic Corporation
Metjahic Safet
Sundaram T. R.
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